Stratix III FPGA Advantages for Video Processing Applications
Stratix® III FPGAs are ideal platforms for meeting the high-performance requirements of your video processing applications while staying within the scope of your design's cost and power budgets.
Implementation of memory intensive video applications is impacted by the amount of available memory and by the memory configuration. Stratix III FPGAs not only have the most amount of embedded memory within their class, but their memory blocks are also very configurable in terms of widths and depths. This can help you fit your design in the smallest device and help you get the optimum signal processing performance.
Figure 1 compares the total amount of embedded memory available in Stratix III FPGAs with competing Virtex-5 devices.
Figure 1. Total Embedded Memory (in Bits) Available in Competing FPGAs
Video applications invariably run out of memory before they run out of logic, but the additional memory available in Stratix III FPGAs will help you fit your design in a smaller and more cost-effective device.
The Stratix III family of FPGAs has significantly more embedded memory available compared to the closest corresponding Virtex-5 devices. In higher density, 200 K logic element (LE) devices, the Stratix III FPGA has almost 1Mbit more available memory than the corresponding Virtex-5 device. In the 300K LE device comparison, the Stratix III FPGA features almost 7 Mbits of additional embedded memory.
As Figure 2 shows, the same advantage holds true when you compare a digital signal processing (DSP) enhanced variant of the Stratix III FPGA with its Virtex-5 counterpart. In almost all cases the Stratix III FPGAs have more available embedded memory than the corresponding Virtex-5 device. Also, DSP-enhanced Stratix III FPGAs provide up to 14.7 Mbits of embedded memory compared to a maximum of just 8.78 Mbits offered in the Virtex-5 DSP-optimized devices.
Figure 2. Total Embedded Memory Bits (in Bits) Available in Competing DSP-Enhanced FPGAs
Even more important than the total amount of embedded memory is the memory block configuration. With the advent of high-definition (HD) video in all spheres of the video market, the line buffer size is standardizing at 1920 pixels (typical HD resolution being 1920 x 1080). Each pixel is generally chroma subsampled at 4:2:2, giving us 20 bits per pixel. The ideal configuration for a video line buffer is a memory block that 20 bits wide and 2 K deep.
The Stratix III FPGA architecture supports M9K blocks that were designed to handle HD video rates. Each M9K block can be configured as 2 K x 4 bits. By cascading 5 of these blocks in parallel (Figure 3) you can implement a video line buffer with a memory bit efficiency of 93.75% (1920/2048).
Figure 3. Cascading M9K Blocks in Parallel
The larger, M144K memory blocks available in Stratix III FPGAs also have a configuration mode of 2048 x 64, making it very easy to build a three line HD buffer as shown in Figure 4.
Figure 4. Three Line HD Buffer
The only bits that are not used are the 4 x 2048 and the 128 bits (2048-1920) x 60 bits out of 64 x 2048 giving a total memory efficiency of 89%
Virtex-5 36 K embedded memory blocks can only take on the following configurations:
32768 X 1
16384 X 2
8192 X 4
4096 X 9
2048 X 18
1024 X 36
These memory block configurations exhibit lower memory efficiency when implementing a typical HD line buffer (1920 pixels with 20 bits/pixel). Consider the 2 K X 18 configuration. A buffer for one HD line created using this configuration would need two instances of the M36K and waste more than 2 K x 16 bits, giving a memory efficiency of less than 55%.
With abundant embedded memory and highly flexible memory configurations, Stratix III FPGAs are ready for use in your next-generation, high-performance HD video processing application.
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