FPGA, CPLD, and ASIC solutions from Altera
  • Download Center
  • Literature
Sign in/register
myAltera Account
Welcome
  •   myAltera
  •   Logout
  • Products
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
    • Literature
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • DSP
    • External Memory
    • Embedded Processing
    • Transceivers
    • Parallel I/O
    • Signal Integrity
    • System Integration
  • Training
    • Training Courses
    • University Program
    • Webcasts & Videos
    • Demonstrations
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Database
    • Devices
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • User Communities/Forums
    • mySupport
  • About Altera
    • About Us
    • Environmental
    • Customer Successes
    • Partners
    • Newsroom
    • Investor Relations
    • Jobs
    • Contact Us
  • Buy Online
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
  • Entire Site
  • Part Number
  • Knowledge Database
  • Support & Technical Docs
  • Forums & Wiki
Username:  
Password:  
 
Forgot my username or password
Don't have myAltera account? Register Now.
Enter your email address:

Stratix III Device Family Architecture

Home > Products > Devices > Stratix III (L and E) > Overview > Stratix III Device Family Architecture

Next Steps

  • View Webcast
  • Download Software
  • Get Training
  • View Video
  • Get Reference Design

Buy Now

  • Purchase Devices

Support

  • Get Device Support
  • View Knowledge Database
  • Purchase Dev Kits
  • Use Troubleshooter
  • Join the Altera Forum

Documentation

  • Get Literature
  • Get Handbook (PDF)
  • Get Data Sheet (PDF)
  • Get White Paper (PDF)
  • Get Email Updates

The core fabric of Stratix® III FPGAs is built from innovative logic units known as adaptive logic modules (ALMs), see Figure 1. The ALMs are routed with the MultiTrack interconnect architecture, enabling Stratix III devices to implement high-speed logic, arithmetic, and register functions.

Adaptive Logic Module

Each ALM has 8 inputs with a fracturable logic structure capable of:

  • A full 6-input look-up table (LUT) or select 7-input LUT
  • Two independent outputs of multiple combinations of smaller LUT sizes for efficient logic packing
  • Implementing complex logic-arithmetic functions without additional resources

Figure 1. Stratix III Device ALM

Figure 1. Stratix III Device ALM

Table 1 details the features and advantages of Stratix III device ALMs.

Table 1. Stratix III Device ALM Features and Advantages
Available Resources per ALM Advantages
8-Input Fracturable LUT
  • Can implement any 6-input logic function and certain 7-input functions and be fractured into independent smaller LUTs, such as two independent 4-input LUTs
  • Quartus® II software design suite integrates this fracturability and optimizes it for performance, efficiency, power, and area (more logic capacity and less wasted logic)
Two Embedded Adders
  • Allows for two two-bit addition, or two three-bit addition without any additional resources
  • Operands can be generated from the same ALM and do not require any additional logic
Two Registers
  • Optimal register-to-logic ratio to ensure device is not register-limited
  • Abundance in registers for register-rich applications or pipeline designs for performance
Two Outputs
  • The inputs of a single ALM can be divided between the two output functions, allowing wide input functions to run fast and narrow input functions to efficiently use remaining resources
MLAB
  • New for the Stratix III FPGA core is a second variation of the logic array block (LAB), known as the MLAB that can be used as a regular ALM or can be configured as simple dual port SRAM blocks
  • Part of the TriMatrix memory technology, MLABs can be configured as a 64x10 or 32x20 simple dual port SRAM blocks. The MLABs have been optimized to implement filter delay lines, small FIFO buffers, and shift registers with maximum performance of 600-MHz clock speeds

For more information, refer to the Logic Array Blocks & Adaptive Logic Modules chapter in the Stratix III Device Handbook.

The MultiTrack Interconnect

Stratix III FPGAs also leverage the MultiTrack interconnect technology. This technology consists of continuous, performance-optimized routing lines of different lengths used for communication within and between distinct design blocks.

MultiTrack interconnect technology shown in Figure 2 is used in Altera's Stratix FPGA series to:

  • Provide the industry's best connectivity with up to five times the logic in a single hop, compared to the competition
  • Provide more accessibility to any surrounding LAB with much fewer connections, thus improving performance and reducing power
  • Avoid area congestion to provide better logic packing

Figure 2. Stratix FPGA Series MultiTrack Interconnect Connectivity

Figure 2. Stratix FPGA Series Multi-Track Interconnect Connectivity

For more information, refer to the MultiTrack Interconnect chapter in the Stratix III Device Handbook.

Advantages of Stratix III Architecture

The fracturable LUT, two full adders, two registers, and additional logic enhancements enable the ALM to be partitioned into two independent LUTs for maximizing efficiency thus making Stratix III the fastest and biggest FPGAs ever—with no wasted logic. Stratix III devices are:

  • 35 percent faster than previous generation Stratix II FPGAs
  • 25 percent faster and can effectively pack 80 percent more logic compared to the nearest competing logic cell. Thereby cutting costs by packing more logic in a smaller, less expensive device
  • Fully integrated with Quartus II software to optimally utilize the 8-input fracturable LUT in the ALM and the MultiTrack routing interconnect architecture, and improve productivity by easily and reliably meeting timing closure

Table 2 provides links to additional information about Stratix III FPGAs.

Table 2. Learn More about Stratix III FPGAs
Topic Description
Stratix III vs. Virtex-5 Stratix III—The World's Fastest FPGAs
Stratix III—The World's Biggest FPGAs
Stratix III vs. Virtex-5 Logic Efficiency
White Papers

Stratix III Programmable Power (PDF)
Stratix III FPGAs vs. Xilinx Virtex-5 Devices: Architecture and Performance Comparison

Technical Papers The Stratix II Logic and Routing Architecture (PDF) (Foundation of Stratix III Architecture)
Improving FPGA Performance and Area Using an Adaptive Logic Module (PDF)
Fracturable FPGA Logic Elements (PDF)
Architecture
ALM Logic Structure's 8-Input Fracturable LUT
Digital Signal Processing (DSP) Blocks
TriMatrix Memory
External Memory Interface

Related Links

  • Defining Stratix II Logic Structure
  • Stratix III Device Family - The Biggest FPGAs in the Industry
  • Stratix III - The World's Fastest FPGAs
Rate This Page


  • Product Selector
    • Compare Devices (Beta)
  • High-End FPGAs
    • About Stratix Series
    • Stratix IV (E, GX, GT)
      • Overview
        • Architecture
        • Density
        • Performance
        • Power
      • Transceivers (GX and GT)
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Stratix III (L and E)
      • Overview
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Stratix II (and GX)
      • Stratix II
        • Overview
        • Design Utilities
        • Features
        • Literature
      • Stratix II GX
        • Overview
        • Design Utilities
        • Features
        • Literature
    • Stratix (and GX)
      • Stratix
        • Overview
        • Design Utilities
        • Features
        • Literature
      • Stratix GX
        • Overview
        • Design Utilities
        • Features
        • Literature
  • Midrange FPGAs
    • About Arria Series
    • Arria II GX
      • Overview
        • Architecture
        • Power
      • Transceivers
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Arria GX
      • Overview
        • Architecture
        • Software
      • Transceivers
      • Applications
      • Design Resources
      • Literature
      • Getting Started
  • Low-Cost FPGAs
    • About Cyclone Series
    • Cyclone IV (E and GX)
      • Overview
        • Architecture
        • Power
      • Transceivers
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Cyclone III (and LS)
      • Overview
        • Architecture
        • Power
        • Security
      • End Markets & Applications
      • Design Resources
      • Literature
      • Getting Started
    • Cyclone II
      • Overview
      • Design Utilities
      • Features
      • Literature
    • Cyclone
      • Overview
      • Design Utilities
      • Features
      • Literature
  • CPLDs
    • About MAX Series
    • MAX II (and G, Z)
      • Overview
        • Architecture
        • Power
        • Unique Features
      • Applications
      • Design Resources
      • Literature
      • Getting Started
    • MAX 3000A
      • Overview
      • Design Utilities
      • Features
      • Literature
  • ASICs
    • About HardCopy Series
    • HardCopy IV (E and GX)
      • Overview
        • Power
        • SEU
        • Performance
      • Transceivers
      • End Markets & Applications
      • Literature
      • Getting Started
    • HardCopy III
      • Overview
        • Architecture
        • Power
        • SEU
        • Performance
      • End Markets & Applications
      • Literature
      • Getting Started
    • HardCopy II
      • Overview
        • Power
        • SEU
        • Performance
      • End Markets & Applications
      • Literature
      • Getting Started
  • Device-Specific Offerings
    • RoHS Compliant
      • Packaging Literature
    • Extended Temperature
    • Enhanced Temperature
    • Military Temperature
  • Configuration Devices
    • Enhanced Configuration
      • Overview
      • Design Utilities
      • Features
      • Literature
    • Serial Configuration
      • Overview
      • Design Utilities
      • Features
      • Literature
  • Mature Products
    • Product Listing
    Please give us feedback
    Products | End Markets | Technology | Training | Support | About Altera | Buy Online
    Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
    Copyright © 1995-2010 Altera Corporation. All Rights Reserved.
    Altera Forum
    Altera
    Forum
    Twitter
    Twitter
    RSS
    RSS
    Facebook
    Facebook
    Flickr
    Flickr
    YouTube
    YouTube
    Email Updates
    Email
    Updates