Altera's Stratix® III FPGAs are the highest density, highest performance 65-nm FPGAs in the industry:
- System designs of unprecedented scale can now be built around Stratix III FPGAs at a lower cost than competitive FPGAs. The largest family member, the EP3SL340 device, features 338,000 equivalent logic elements (LEs), over 17 Mbits of on-chip memory, 576 embedded 18 x 18 multipliers, and up to 1,056 user I/O pins. This device has 17 percent more logic and 66 percent more dedicated memory than any other 65-nm FPGA.
- For DSP intensive applications, the EP3SE110 device offers up to 896 embedded 18x18 multipliers, offering close to 500 GMAC/s and 75 percent more DSP resources than any other 65-nm FPGA.
All these Stratix III FPGA density benefits are enabled by Quartus® II design software, which is optimized to provide the highest level of productivity for complex designs.
Logic Density Advantage
The basic logic structure of a Stratix III FPGA is an adaptive logic module (ALM), while the basic logic structure of a Virtex-5 FPGA is a LUT-FF pair. To provide a fair comparison, benchmark analysis was conducted on over 65 customer designs using Synplify Pro software version 8.6.1, Quartus II software version 6.0, and ISE software version 8.2i service pack 1. The method used fixed performance with optimizations for area. The results are shown in Figure 1.
Figure 1. Stratix III ALM vs. Virtex-5 LUT-FF Pair Logic Density Benchmark
On average, one Stratix III ALM is equivalent to 1.8 Virtex-5 LUT-FF pairs. Therefore, a Stratix III EP3SL340 device (with 135,000 ALMs) has 17 percent more logic capacity than a Virtex-5 XC5VLX330 (with 207,360 LUT-FF pairs).
Quartus II Delivers Highest Level of Productivity
The Quartus II design software includes many advanced features such as the SOPC Builder system-level design tool, incremental compilation, team-based design environment, TimeQuest timing analyzer, and PowerPlay power analysis and optimization tools, all working together to make complex system-level design easier and faster.
Redundancy Improves Yield and Availability
With Altera's patented redundancy technology, defects in one column can be easily fixed by turning on the redundant column in the Stratix III device. Large Altera® devices, like Stratix III FPGAs, that could be highly susceptible to the early yield variability of a new process can be reliably manufactured using this unique redundancy technology which has, in some cases, improved yields more than fivefold.
Benefits to Designers
Over the years, Altera has established an excellent track record of delivering high-density FPGAs on schedule and in volume. Stratix III FPGAs offer the highest productivity and lowest risk for high-density designs, and are well suited for a variety of applications including ASIC prototyping.
By using the highest density FPGA in the industry, you can emulate a complete ASIC in fewer FPGAs, increase performance, and reduce emulation board complexity. You can achieve additional cost reduction for high-volume designs simply by migrating to Altera’s HardCopy® ASICs.
For additional information about the benefits of Stratix III FPGAs, visit the links listed in table 1.
| Table 1. Learn More About Stratix III FPGAs | |
| Topic | Description |
|---|---|
| Stratix III vs. Virtex-5 | Stratix III–The World’s Fastest 65-nm FPGAs |
| Stratix III vs. Virtex-5 Logic Efficiency | |
| Architecture | Stratix III Device Family Architecture Advantage |
| Stratix III ALM Logic Structure's 8-Input Fracturable LUT | |
