Stratix III FPGA High-Performance DSP Features
Stratix® III FPGAs are a great solution for high-performance digital signal processing (DSP) system requirements. When compared with DSP processors, Stratix III FPGAs deliver:
- More DSP performance
- Lower cost
- Lower power consumption
- Smaller board space
- More platform scalability
Table 1 shows how you can use a single Stratix III FPGA to replace multiple DSP processors.
| Table 1. Comparison of a Stratix III FPGA to Leading Performance DSP Processors |
| Device Type |
Stratix III EP3SL70 |
TI C64x |
| Clock Frequency |
300 MHz |
1 GHz |
| Number of Devices |
1 |
10 |
| Total GMACS |
86 |
80 |
| Total Power |
~3 watts |
~10–15 watts |
| Total Board Area |
~1.225 mm2 |
~ 5.000 mm2 |
| Total Cost |
$400
(1 x $400 @ 1 K units) |
$3000
(10 x $300 @ 1 K units) |
DSP Coprocessing with Stratix III FPGAs
You can use Stratix III FPGAs to implement complete, high-throughput DSP systems, and you can use them as FPGA coprocessors. In coprocessor applications, Stratix III FPGAs accelerate performance-critical DSP functions that would otherwise consume a majority of the host processor's processing power, and slow down overall system performance.
When used as coprocessors, Stratix III FPGAs boost overall system performance by offloading complex computations such as multiple-input multiple-output (MIMO) processing, multi-user detection, echo cancellation, and correlators from the host processor.
Altera offers a broad range of support services, tools, and development platforms for implementing DSP designs in Stratix III FPGAs. You can quickly develop Stratix III devices into user-defined FPGA coprocessors as well using DSP Builder, Altera's data-flow architecture development tool based on the industry-leading MATLAB and Simulink tools from The MathWorks.
Once the coprocessor architecture is captured, it can automatically be implemented into an Altera® Stratix III FPGA or exported to Altera's SOPC Builder system development tool for further integration into the overall system architecture.
Altera also offers DSP development kits that can be used to verify your DSP systems in hardware in the prototype phase of your design cycle.
Platform Scalability
Stratix III FPGAs support vertical package migration from small to large devices. This enables a single board design to scale from a small Stratix III FPGA, like the EP3SE50, to the industry’s highest performance FPGA for DSP processing, the EP3SE110, which is capable of nearly 500 giga multiply-accumulate operations per second (GMACS). This range of scalability is possible because of the parallel processing nature of the Stratix III FPGA family. Table 2 illustrates the DSP performance capability of a small Stratix III FPGA.
| Table 2. Stratix III DSP Block Parallel Processing Performance |
| Device Type |
Stratix III EP3SE50 |
| Total 18 x 18 Multipliers |
384 |
| Maximum Clock Frequency |
550 MHz |
| Maximum Performance |
384 Multipliers at 550 MHz = 211 GMACS |
Stratix III FPGAs are ideal for video and image processing, high-speed digital communications, and other high-performance DSP applications. Optimized DSP blocks in Altera's Stratix III FPGAs combine with TriMatrix memory and adaptive logic modules (ALMs) to unleash the highest DSP performance in the industry.
At nearly 500 GMACS, the DSP throughput of Stratix III devices is orders of magnitude higher than any single-chip DSP processor available, easily meeting the requirements of the emerging standards and protocols shown in Table 3.
| Table 3. DSP Applications That Can Be Implemented Using Stratix III DSP Blocks |
| Applications |
Military Applications |
Image Processing |
Communications |
| Radar/Sonar |
Broadcast and Medical |
Wireless |
| Algorithms and Functions |
- Filtering
- Transforms
- Modulation
|
- Filtering
- Compression
- Scaling
|
- Chip-rate processing
- Equalization
- Digital IF (DDC, DUC)
|
| Standards and Protocols |
- |
|
- HSDPA, HSUPA
- MBMS, EDCH
- CDMA 2000, 1x EVDV
- OFDMA
- WiMAX (802.16d/e)
|
DSP Block Details
The Stratix III DSP block is a high-performance silicon architecture with great programmability that delivers optimized processing across many applications. Each DSP block provides eight 18 x 18 multipliers, as well as registers, adders, subtractors, accumulators, and summation unit-functions that are frequently required in typical DSP algorithms. The DSP block supports completely variable bit-widths and various rounding and saturation modes to efficiently meet the exact requirements of your application.
Figure 1. DSP Block Architecture
Table 4 shows the DSP resources of Stratix III FPGAs.
| Table 4. Stratix III FPGA DSP Resources |
| Stratix III Family Variant |
Device |
Multipliers |
| 9 x 9 |
12 x 12 |
18 x 18 |
36 x 36 |
18 x 18 Complex |
18 x 18 Sum of Multipliers |
| Stratix III L |
EP3SL50 |
216 |
162 |
108 |
54 |
54 |
216 |
| EP3SL70 |
288 |
216 |
144 |
72 |
72 |
288 |
| EP3SL110 |
288 |
216 |
144 |
72 |
72 |
288 |
| EP3SL150 |
384 |
288 |
192 |
96 |
96 |
384 |
| EP3SL200 |
576 |
432 |
288 |
144 |
144 |
576 |
| EP3SL340 |
576 |
432 |
288 |
144 |
144 |
576 |
| Stratix III E |
EP3SE50 |
384 |
288 |
192 |
96 |
96 |
384 |
| EP3SE80 |
672 |
504 |
336 |
168 |
168 |
672 |
| EP3SE110 |
896 |
672 |
448 |
224 |
224 |
896 |
| EP3SE260 |
768 |
576 |
384 |
192 |
192 |
768 |
As with previous generation Stratix devices, Quartus® II software continues to deliver optimal mapping of your DSP algorithms to the Stratix III ALM fabric, the TriMatrix memory, and the DSP blocks from HDL-specific and DSP-specific development tools and libraries.
See how Stratix III DSP capabilities stack up with other FPGAs
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