Stratix III FPGA I/O Pin Connectivity
Stratix® III FPGA I/O pins have the system-level performance and flexibility required to communicate with a multitude of devices. Intellectual property (IP) cores and software tools such as the TimeQuest timing analyzer, Early simultaneous switching noise (SSN) Estimator, and Pin Planner aid in ease of use and rapid integration.
|
Table 1. Stratix III High-Speed True-LVDS Data Rates
|
| Speed Grade |
C2 |
C3 / I3 |
C4 / I4L |
| Data Rate |
1.6 Gbps |
1.25 Gbps |
1.04 Gbps |
| Table 2. Stratix III FPGA I/O Pin Connectivity Overview |
| Feature |
Details |
| LVDS Support on all I/O Pin Banks |
- Up to 132 full-duplex, 1.25-Gbps, true-LVDS channels
(132 Tx + 132 Rx) on the side I/O pin banks.
- Up to 288 lower speed pseudo LVDS channels on top and bottom I/O pin banks
|
| DDR Support on all I/O Pin Banks |
- Up to 31 hard I/O pin registers behind each DQ pin for best-in-class DDR support
- Up to 1067 Mbps (533 MHz) support on top and bottom I/O pin banks
- Up to 667 Mbps (333 MHz) support on side I/O pin banks
|
| Independent Banks |
- Up to 24 independent user I/O pin banks provide flexible and efficient pin usage
- Common bank structure for vertical migration
|
Differential Signaling with Stratix III FPGAs
Stratix III FPGA I/O pins support high-performance, DC-coupled LVDS transmit and receive channels on the side I/O pins with additional lower speed LVDS support on the top and bottom banks. Every high-speed, side I/O LVDS pin pair has a hard dynamic phase alignment (DPA) block to eliminate clock-to-channel and channel-to-channel skew, as shown in Figure 1. Stratix III FPGA high-speed LVDS I/O pins support interface standards such as SPI-4.2, SFI-4, SGMII, Utopia IV, 10 GbE XSBI, RapidIO®, and SerialLite.
| Table 3. Stratix III FPGA Differential Signaling I/O Pin Feature Overview |
| Feature |
Details |
| High-Speed LVDS |
- Hard DPA block with serializer/deserializer (SERDES) and clock-forwarding capability for soft-CDR
- Programmable pre-emphasis and Voltage Output Differential (VOD)
- Differential on-chip termination (OCT)
|
Figure 1. Hard DPA and SERDES Block with Clock-Forwarding Capability on Stratix III FPGAs
For more information on differential signaling see the High-Speed Differential I/O Interfaces with DPA in Stratix III Devices (PDF) chapter of the Stratix III Device Handbook.
Single-Ended I/O Support on Stratix III FPGAs
Stratix III FPGA I/O pins support single-ended I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X.
| Table 4. Stratix III FPGA Single-Ended I/O Pin Feature Overview |
| Feature |
Details |
| Single-Ended I/O Pin |
- Programmable slew rate and drive strength
- Dynamic trace compensation (variable delay chains for board trace mismatch compensation on both input and output signals)
- Serial, parallel, and dynamic OCT
|
For more information on OCT see Termination Solutions in Stratix III Devices.
| Table 5. Stratix III FPGA Differential and Single Ended I/O Pin Support |
| I/O Pin Standards |
Performance Target (1) |
Typical Application |
Comments |
| Differential I/O Pins |
| LVDS |
1.6 Gbps |
Chip-to-chip |
OCT |
| Differential HSTL |
400 MHz |
Memory |
OCT |
| Differential SSTL |
400 MHz |
Memory |
OCT |
| LVPECL |
350 MHz |
General Purpose |
Clock Inputs Only |
| Single-Ended I/O Pins |
| 3.0-V/2.5-V/1.8-V LVTTL |
167 MHz |
General Purpose |
Impedance Matching |
| 3.0-V/2.5-V/1.8-V/1.5-V/1.2-V LVCMOS |
167 MHz |
General Purpose |
Impedance Matching |
| SSTL-2 Class I and II |
250 MHz |
Memory |
Serial and Parallel OCT |
| SSTL-15 Class I and II |
533 MHz |
Memory |
Serial and Parallel OCT |
| SSTL-18 Class I and II |
400 MHz |
Memory |
Serial and Parallel OCT |
| 1.8-V/1.5V/1.2-V HSTL I and II |
400 MHz |
Memory |
Serial and Parallel OCT |
| 3.0-V PCI |
66 MHz |
PC, Embedded |
Impedance Matching |
| 3.0-V PCI-X 1.0 |
133 MHz |
PC, Embedded |
Impedance Matching |
Note:
- Pending characterization
For more information on I/O pin standards see the I/O Pin Interfaces (PDF) chapter of the Stratix III Device Handbook.
Stratix III FPGA High-Speed External Memory Interface Support
Stratix III FPGA I/O pins support existing and emerging external memory standards such as DDR, DDR2, DDR3, QDRII, QDRII+ and RLDRAMII at frequencies up to 400 MHz. A self-calibrating data path takes advantage of the new I/O pin structure, dynamically adjusting itself to always provide the highest reliable frequency of operation across process, voltage and temperature.
| Table 5. Stratix III FPGA External Memory Interfaces I/O Pin Feature Overview |
| Feature |
Details |
| External Memory Support |
- Single data rate (SDR) and half data rate (HDR – half the frequency and twice the data width of SDR) input and output options
- HDR block with alignment and synchronization
- De-skew, read/write leveling and clock-domain crossing functionality
|
| Table 6. Stratix III FPGA External Memory Interface Performance (1) |
| Memory Standard |
I/O Pin Standard |
Maximum Clock Speed |
Maximum Data Rate |
| DDR SDRAM |
SSTL-2 |
200 |
400 Mbps |
| DDR2 SDRAM |
SSTL-1.8 |
400 |
800 Mbps |
| DDR3 |
SSTL-1.5 |
533 |
1067 Mbps |
| QDRII |
1.8v / 1.5v HSTL |
350 |
1400 Mbps |
| QDRII + |
1.8v / 1.5v HSTL |
350 |
1400 Mbps |
| RLDRAMII |
1.8v HSTL |
400 |
800 Mbps |
Note:
- Pending characterization
For more information on external memory interfaces on Stratix III FPGAs, see Altera's External Memory Solution Center and the External Memory Interfaces in Stratix III Devices chapter of the Stratix III Devices Handbook.
Stratix III FPGA Signal Integrity
Stratix III FPGA I/O pin banks deliver best-in-class signal integrity, low SSN and superior eye quality through many chip- and package-level enhancements.
| Table 7. Stratix III FPGA Signal Integrity I/O Pin Feature Overview |
| Feature |
Details |
| Signal Integrity |
- 8:1:1 User I/O pin to power/ground ratio
- Optimized signal return paths
- Staggered output delay control
- Optimized on-die and on-package decoupling
|
Related Links
|
 Next Steps
Buy Now
Support
Documentation
|
Literature
> 
