Single Event Upset Mitigation in Stratix Series FPGAs
In many applications, especially high-reliability applications, the ability to detect and act upon single event upsets (SEUs) while an FPGA is operating has become more important than ever before. Altera's Stratix® series of high-end FPGAs offers a range of features and solutions designed to mitigate the effects of SEUs and achieve or surpass system reliability goals.
Configuration Error Checking
Dedicated cyclical redundancy check (CRC) background configuration checker circuitry was introduced by Altera in the first generation of Stratix FPGAs. Since then, Altera has enhanced the capability of dedicated CRC circuitry in a number of ways:
- Instead of a single CRC value for the entire device, Stratix series FPGAs (in Stratix III FPGAs and later)store a CRC value each for configuration frame, thereby allowing faster SEU detection
- The CRC error detection engine in Stratix series FPGAs (Stratix III FPGAs and later) provides the location of the SEU for both single and adjacent multiple bit-errors
- The CRC configuration circuit in Stratix series FPGAs (Stratix III FPGAs and later) allows for various types of error injection to simulate SEU events and test mitigation strategy
Figure 1. Enhanced CRC Configuration Error Checker in Stratix III and Later Stratix Series FPGAs
Critical Error Determination
Since the majority of configuration errors have no effect on the functionality of an FPGA, the ability to ignore these "don't care" soft errors provides a step increase in the actual mean time between failures (MTBFs) from SEUs. Using the location data provided by the enhanced CRC circuit in found in Stratix III and later Stratix series FPGAs, and a small amount of logic to check the error location against the criticality map, an SEU can be determined to be "care" or "don’t care" as shown in Figure 1.
In the event of a "don’t care" configuration error, you can decide to ignore the SEU and continue running. The criticality map is automatically generated by the Quartus® II development tool, and is accessed via a user defined interface, such as the active serial configuration memory. The criticality processor logic will be supplied as a reference design in future versions of Quartus II software and features triple module redundancy techniques for maximum integrity.
Figure 2. Critical Configuration Error Detection in Stratix III and Later Stratix Series FPGAs
On-Chip Memory Error Checking
In addition to configuration memory checking, Stratix series FPGAs (in Stratix III FPGAs and later) offer the ability to check the integrity of on-chip memory. Using the ninth memory bit, along with automatically generated error correction coding (ECC) circuits, both the MLAB and M9K blocks provide SEU mitigation. The M144K blocks also offer this functionality, except that the ECC circuit is included in hard gates within the memory block.
Using ECC, each of the three on-chip memory block types can detect up to two-bit errors and correct single-bit errors automatically. Configuration of ECC functionality is made simple via the MegaWizard® Plug-In Manager found within the Quartus II software.
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