Stratix III TriMatrix Memory
Stratix® III TriMatrix on-chip memory offers maximum efficiency and flexibility, and is an enhancement based upon the Stratix II FPGA TriMatrix memory:
- Up to 17 Mbits of total memory (in M9K and M144K blocks)
- Clock rates of up to 600 MHz for total bandwidth in excess of 25 Terabits per second
- Logic array block (LAB)-based MLAB blocks for small grain distributed memory resources
- Power-down modes based on Altera’s Programmable Power Technology
- Advanced features such as error code correction (ECC)
- For memory intensive applications, Stratix III E devices offer more memory and digital signal processing (DSP) blocks per logic
Figure 1. TriMatrix Memory Structure
Each MLAB is implemented using one LAB containing 10 adaptive logic modules (ALMs). Half the LABs in a Stratix III device can be configured as MLABs. The M9K and M144K blocks are dedicated memory resources. The Stratix III FPGA Family Overview lists memory resources for each Stratix III device.
Maximum Memory Efficiency and Bandwidth
By offering three different memory block sizes, you can select the best fit for your applications. TriMatrix memory significantly improves memory utilization and reduces the need for memory cascading. The MLAB and M9K blocks allow Stratix III devices to offer more data ports or memory bandwidth than other FPGAs. Table 1 shows how you can use TriMatrix memory to address a variety of memory applications.
| Table 1. TriMatrix Memory Application Examples |
| Memory Block |
Applications |
| MLAB |
- Shift registers
- Small FIFO buffers
- Filter delay lines
|
| M9K |
- General-purpose memory
- Packet header or cell buffers
|
| M144K |
- Processor code storage
- Packet buffers
- Video frame buffers
|
Advanced Memory Features
TriMatrix memory incorporates many advanced features:
- Simple and true dual-port modes
- Packed mode allowing each M9K or M144K block to be split into two half-size memories
- M144K blocks contain a dedicated ECC feature to detect and correct soft errors
- ECC can be implemented using logic for the MLAB and M9K blocks
- Unused memory blocks are automatically put into the low power mode, providing more power savings
Table 2 shows the advanced memory features of Stratix III TriMatrix memory.
| Table 2. TriMatrix memory features |
| Feature |
MLAB
640 Bits |
M9K
9,216 Bits |
M144K
147,456 Bits |
| Performance |
600 MHz |
600 MHz |
600 MHz |
| Depth x Maximum Width |
32 x 20 |
256 x 36 |
2,048 x 72 |
| Simple Dual-Port |
Yes |
Yes |
Yes |
| True Dual-Port |
No |
Yes |
Yes |
| Parity |
Yes |
Yes |
Yes |
| ECC |
Yes |
Yes |
Yes |
| Packed Mode |
No |
Yes |
Yes |
| Low Power Mode |
Yes |
Yes |
Yes |
| Shift Register |
Yes |
Yes |
Yes |
| FIFO |
Yes |
Yes |
Yes |
| Initialization |
Yes |
Yes |
Yes |
| Mixed-Clock |
Yes |
Yes |
Yes |
| Byte Enable |
Yes |
Yes |
Yes |
| Address Clock Enable |
Yes |
Yes |
Yes |
The Stratix III FPGA Family Overview lists memory resources for each Stratix III device.
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