Quartus® II software delivers the #1 performance and productivity for high-density, high-performance, and low-power Stratix® III FPGA designs. Quartus II software allows you to exceed your performance goals, complete your design faster, and meet power budgets for your Stratix III designs. Advanced place-and-route technology, physical synthesis, and the TimeQuest timing analyzer help you quickly close timing. Using the industry’s first and most comprehensive incremental compilation feature, you can reduce your design cycle with shorter compile times. Lastly, PowerPlay power analysis and optimization technology automatically minimizes your design’s power consumption.
The Leader in Productivity for High-Density, High-Performance FPGA Designs
Quartus II software can dramatically improve your productivity compared to traditional high-density FPGA design flows by using the following productivity-enhancing features:
- TimeQuest timing analyzer is an ASIC-strength timing analyzer with native support for the industry-standard SDC timing constraints format. The TimeQuest timing analyzer offers an easy-to-use GUI, SDC editor, and tool command language (Tcl) console to quickly and easily create timing constraints. In addition, the TimeQuest timing analyzer offers fast, interactive timing analysis and reporting to quickly reach timing closure.
- Incremental compilation is an industry first. This feature supports top-down and bottom-up, team-based design which delivers faster compilation times for design iterations while preserving performance.
- PowerPlay power analysis and optimization technology provides automated power optimization capabilities and helps you effectively manage power from design concept through implementation. It includes support for Stratix III Programmable Power Technology.
- SOPC Builder is a system-level tool that eliminates mundane and error-prone system integration tasks and allows you to build systems in minutes.
- Push-button physical synthesis technology and the automated Design Space Explorer simplifies design optimization.
- Extensive cross-probing support between tools helps identify and correct design issues.
- The pin planner feature (PDF) enables easy I/O pin assignment planning, assignment, and validation.
- Complete command-line and Tcl scripting interfaces give you advanced scripting capabilities.
- Industry-leading compile times in Quartus II software are the lowest in the industry.
- Multi-processor support in Quartus II software now supports parallel processing during compilation for computers with multiple processors. You can reduce compile times by up to 15 percent.
- Memory requirements in Quartus II software typically are half the memory required by competing solutions, allowing you to avoid an "out of memory" error during compilation.
- Quartus II software is now built in 32-bit and 64-bit versions for Windows operating systems. Quartus II 64-bit application software allows you to take advantage of computers with more than 4 Gbytes of memory when running Windows XP professional x64.
- Verification solutions include the following features:
- Capability to update memory and constants in-system without reconfiguring the device.
- Chip Planner shows hierarchical views of a design implemented in an Altera® device.
- SignalTap® II embedded logic analyzer and support for integration with external logic analyzers.
- Integration with all leading third-party EDA verification tools and methodologies.
The Leader in Performance for High-Density, High-Performance FPGA Designs
Quartus II software enables the highest levels of performance and the fastest path to design completion for high-density Stratix III FPGA designs. Quartus II software and Stratix III FPGAs offer a significant performance advantage compared to other high-density FPGA and software solutions:
- Stratix III FPGAs and Quartus II software offer the highest performance in the industry.
- Advanced Place-&-Route Algorithms offer the fastest push-button results in the industry.
- The Quartus II software's Design Space Explorer (PDF) script increases average design performance by 20 percent, automatically applying combinations of netlist optimizations and advanced Quartus II software compiler settings.
- The Quartus II software's physical synthesis can re-wire logic connections, duplicate registers, and move registers to significantly improve overall circuit performance.
- Optimized to operate at over 200 MHz, the Nios® II/f "fast" processor is designed for maximum performance.
Only Parallel Development for FPGAs and HardCopy ASICs
Only the Quartus II software provides seamless migration between Stratix III FPGA designs and HardCopy® series ASIC designs. By enabling compilation for HardCopy series ASIC devices, Quartus II software provides the only risk-free path to higher performance and lower device costs.
Getting Started with Stratix III FPGAs and Quartus II Software
Stratix III devices are supported in the Quartus II software version 6.1. Download the Quartus II Subscription Edition software and start designing your Stratix III FPGAs today with the included free 30-day trial. To purchase an Altera subscription package, contact your local distributor or sales representative.
