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Stratix IV White Papers

Home > Products > Devices > Stratix IV (E, GX, GT) > Design Resources > Stratix IV White Papers

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The white papers shown in Table 1 are available to help you make system design decisions and evaluate the benefits of Altera's 40-nm solutions with Stratix® IV FPGAs, HardCopy® IV ASICs, and Quartus® II software.

Table 1. Stratix IV FPGA White Papers
Category Description
General
Leveraging the 40-nm Process Node to Deliver the World's Most Advanced Custom Logic Device (PDF) This paper discusses 40-nm process benefits over prior nodes, including the 65-nm node and the more recent 45-nm node.
Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (PDF) Discusses how Altera's 40-nm transceiver innovations enable superior jitter, noise, signal integrity, and BER performance at the minimum power.
40-nm Power Management and Advantages (PDF) Learn how 40-nm benefits and Altera's patented Programmable Power Technology enable the lowest power for high-end FPGAs and HardCopy ASICs.
Related White Papers
Increasing Productivity With Quartus II Incremental Compilation (PDF) This paper describes how an incremental compilation flow can improve your productivity when designing for high-density, high-performance FPGAs.
Guidance for Accurately Benchmarking FPGAs (PDF) This paper presents a rigorous methodology for accurately benchmarking the capabilities of an FPGA architecture.
Basic Principles of Signal Integrity (PDF) Learn how to overcome signal integrity issues by following good design techniques and simple layout guidelines described in this document.
Performing Equivalent Timing Analysis Between Altera TimeQuest and Xilinx Trace (PDF) This paper covers the differences in timing analysis between Altera’s TimeQuest timing analyzer and Xilinx’s Trace, and explains how to configure the tools to provide equivalent performance comparison.
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