Literature Licensing Buy On-Line Download Entire Site Part Number Knowledge DB

Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line

Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature

High-End FPGAs       About Stratix Series    Stratix IV (E and GX)        Overview           Transceivers (GX)           End Markets & Applications           Design Resources           Literature           Getting Started    Stratix III (L and E)    Stratix II (and GX)    Stratix (and GX)     Midrange FPGAs    Arria (GX)     Low-Cost FPGAs    Cyclone III    Cyclone II    Cyclone     CPLDs    MAX II (and G, Z)    MAX 3000A     ASICs       About HardCopy Series    HardCopy IV (E and GX)    HardCopy III    HardCopy II    HardCopy Stratix     Device-Specific Offerings    RoHS Compliant       Extended Temperature       Enhanced Temperature       Military Temperature     Configuration Devices    Enhanced Configuration    Serial Configuration     Mature Products       Product Listing

Home > Products > Devices > Stratix IV (E and GX) > Literature Print This Page Subscribe to Email Literature: Stratix IV Devices Package Specifications Thermal Specifications Device Pinouts Pin Connection Guidelines Known Stratix® IV Issues Family Overview (PDF) Datasheet (PDF) Upcoming Device Features (PDF) BSDL Files Stratix IV Device Handbook (15 MB) Show All / Hide All Volume 1 - Stratix IV Device Handbook (ver 2.0, Nov 2008, 4 MB) Section I. Device Core (2 MB) Chapter 1. Stratix IV Device Family Overview (ver 2.0, Nov 2008, 205 KB) Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices (ver 2.0, Nov 2008, 237 KB) Chapter 3. TriMatrix Embedded Memory Blocks in Stratix IV Devices (ver 2.0, Nov 2008, 277 KB) Chapter 4. DSP Blocks in Stratix IV Devices (ver 2.0, Nov 2008, 377 KB) Chapter 5. Clock Networks and PLLs in Stratix IV Devices (ver 2.0, Nov 2008, 745 KB) Section II. I/O Interfaces (2 MB) Chapter 6. I/O Features in Stratix IV Devices (ver 2.0, Nov 2008, 664 KB) Chapter 7. External Memory Interfaces in Stratix IV Devices (ver 2.0, Nov 2008, 549 KB) Chapter 8. High Speed Differential I/O Interfaces with DPA in Stratix IV Devices (ver 2.0, Nov 2008, 516 KB) Section III. System Integration (1 MB) Chapter 9. Hot Socketing and Power-On Reset in Stratix IV Devices (ver 2.0, Nov 2008, 108 KB) Chapter 10. Configuration, Design Security, Remote System Upgrades with Stratix IV Devices (ver 2.0, Nov 2008, 836 KB) Chapter 11. SEU Mitigation in Stratix IV Devices (ver 2.0, Nov 2008, 177 KB) Chapter 12. JTAG Boundary Scan Testing (ver 2.0, Nov 2008, 107 KB) Chapter 13. Power Management in Stratix IV Devices (ver 2.0, Nov 2008, 144 KB) Volume 2 - Stratix IV Device Handbook (ver 2.0, Nov 2008, 7 MB) Section I. Transceiver Architecture (7 MB) Chapter 1. Stratix IV Transceiver Architecture (ver 2.0, Nov 2008, 3 MB) Chapter 2. Stratix IV Transceiver Clocking (ver 2.0, Nov 2008, 2 MB) Chapter 3. Configuring Multiple Protocols and Data Rates (ver 2.0, Nov 2008, 358 KB) Chapter 4. Reset Control and Power Down (ver 2.0, Nov 2008, 792 KB) Chapter 5. Stratix IV Dynamic Reconfiguration (ver 1.0, Nov 2008, 2 MB) Volume 3 - Stratix IV Device Handbook (ver 2.0, Nov 2008, 3 MB) Section I. Transceiver Configuration Guide (3 MB) Chapter 1. ALTGX Transceiver Setup Guide (ver 2.0, Nov 2008, 2 MB) Chapter 2. Transceiver Design Flow Guide (ver 2.0, Nov 2008, 770 KB) Chapter 3. Porting a Stratix II GX Transceiver Design to a Stratix IV GX Device (ver 1.0, Nov 2008, 192 KB) Chapter 4. Stratix IV ALTGX_RECONFIG Megafunction User Guide (ver 1.0, Nov 2008, 237 KB) Volume 4 - Stratix IV Device Datasheet (ver 2.0, Nov 2008, 985 KB) Section I. Stratix IV Device Datasheet (440 KB) Chapter 1. DC and Switching Characteristics (ver 2.0, Nov 2008, 864 KB) Related Documentation External Memory Interfaces AN 408: DDR2 Memory Interface Termination, Drive Strength, Loading, and Design Layout Guidelines (ver 2.1, Jul 2008, 4 MB)      SII Simulation Example (3 KB)      SIII Simulation Example (3 KB) AN 435: Using DDR and DDR2 SDRAM with Stratix III and Stratix IV Devices (ver 2.0, Aug 2008, 2 MB)      AN 435 Design Files (3 MB) AN 436: Using DDR3 SDRAM with Stratix III and Stratix IV Devices (ver 4.0, Nov 2008, 2 MB)      AN 436 Design Files (11 MB) AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix IV, Stratix III, and Cyclone III Devices (ver 4.0, Sep 2008, 624 KB)      SIII_phase_shift (5 KB) AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III Devices (ver 1.1, Jul 2008, 1 MB)      Design Example for AN 461 (2 MB) AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines (ver 1.0, Jun 2008, 918 KB) External DDR Memory PHY Interface Megafunction User Guide (ALTMEMPHY) (ver 5.0, Jul 2008, 2 MB) Power and Thermal Management 40-nm FPGA Power Management and Advantages (ver 1.1, Oct 2008, 2 MB) Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB) AN 514: Power Optimization in Stratix IV FPGAs (ver 1.0, May 2008, 221 KB) Power Delivery Network (PDN) Tool User Guide (ver 1.0, May 2008, 963 KB)      Power Delivery Network (PDN) Tool (1 MB) PowerPlay Early Power Estimator User Guide For Stratix III and Stratix IV FPGAs (ver 2.0, May 2008, 1 MB) Stratix III and Stratix IV PowerPlay Early Power Estimator (ver 8.1, Nov 2008, 18 KB)      PowerPlay Early Power Estimator User Guide For Stratix III and Stratix IV FPGAs (1 MB) Voltage Regulator Selection for FPGAs (ver 1.0, Nov 2008, 306 KB) I/O Interfaces, Protocols and Signal Integrity AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing (ver 1.0, May 2008, 1 MB) AN 529: Via Optimization Techniques for High-Speed Channel Designs (ver 1.0, May 2008, 690 KB) AN 530: Optimizing Impedence Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs (ver 1.0, May 2008, 208 KB) PCI Express Compiler User Guide (ver 8.1, Nov 2008, 3 MB) Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB) AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines (ver 1.0, Jun 2008, 918 KB) PCI Express hard intellectual property solutions from Altera (ver 1.0, Jul 2008, 165 KB) Triple Speed Ethernet MegaCore Function User Guide (ver 8.1, Nov 2008, 1 MB) DSP 40-nm Stratix IV FPGAs and HardCopy IV ASICs (ver 1.1, Sep 2008, 372 KB) Design Guidelines AN 519: Stratix IV Design Guidelines (ver 1.0, Aug 2008, 799 KB) AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III Devices (ver 1.1, Jul 2008, 1 MB)      Design Example for AN 461 (2 MB) AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines (ver 1.0, Jun 2008, 918 KB) Stratix IV GX Device Family Pin Connection Guidelines (ver 1.0, Oct 2008, 156 KB) Development Kits Altera Product Catalog (ver 5.0, Jul 2008, 2 MB) End Applications 40-nm FPGAs and the Defense Electronic Design Organization (ver 1.0, Jul 2008, 313 KB) Anti-Tamper Capabilities in FPGA Designs (ver 1.0, Jul 2008, 310 KB) DO-254 Support for FPGA Design Flows (ver 1.0, Jul 2008, 91 KB) DO-254-certifiable IP cores (ver 2.0, Nov 2008, 119 KB) HardCopy ASICs (ver 1.1, Jul 2008, 277 KB) Military Benefits of the Managed Risk Process at 40 nm (ver 1.0, Jul 2008, 993 KB) Military Productivity Factors in Large FPGA Designs (ver 1.0, Jul 2008, 443 KB) General Device Documentation 40-nm Stratix IV FPGAs and HardCopy IV ASICs (ver 1.1, Sep 2008, 372 KB) Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers (ver 1.0, May 2008, 3 MB) HardCopy ASICs (ver 1.1, Jul 2008, 277 KB) Leveraging the 40-nm Process Node to Deliver the World's Most Advanced Custom Logic Devices (ver 1.0, May 2008, 371 KB) Training Courses Serial RapidIO Design with Stratix IV GX FPGAs Ethernet Design with Stratix IV GX FPGAs PCI Express Design with Stratix IV GX FPGAs Rate This Page

Please Give Us Feedback

Home | Products | Support | End Markets | Technology Center | Education & Events | Corporate | Buy On-Line  Devices | Design Software | Intellectual Property | Design Services | Dev. Kits/Cables | Literature  Contact Us | Site Help | Site Map | Privacy | Legal Notice  Copyright © 1995-2008 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus and MegaCore are trademarks of Altera Corporation