Stratix IV FPGA High-Performance DSP Features
Stratix® IV FPGAs are a great solution for high-performance digital signal processing (DSP) system requirements. When compared with DSP processors, Stratix IV FPGAs deliver:
- More DSP performance
- Lower cost
- Lower power consumption
- Smaller board space
- More platform scalability
Table 1 shows how you can use a single Stratix IV FPGA to replace multiple DSP processors.
| Table 1. Comparison of a Stratix IV FPGA to Leading Performance DSP Processors |
| Specification |
Stratix IV EP4SGX70 |
Texas Instruments C64x |
| Clock Frequency |
400 MHz (max 550 MHz) |
1.2 GHz |
| Number of Devices |
1 |
30 |
| Total GMACS (1) |
153 (max 708 in EP4SGX230) |
144 |
| Total Power |
~3 watts |
~68 watts
30 x (1.76W core + 0.53W I/O) @ 50% utilization |
| Total Board Area |
~1,225 mm2 |
~ 15,000 mm2 |
| Total Cost |
$209
(1 x $209 @ 1 K units) |
$9,000
(30 x $300 @ 1 K units) |
Note:
-
GMACS = giga multiply-accumulate operations per second
Stratix IV FPGAs Do the Heavy DSP Lifting
You can use Stratix IV FPGAs to implement complete, high-throughput DSP systems, and you can use them as FPGA coprocessors. In coprocessor applications, Stratix IV FPGAs accelerate performance-critical DSP functions that would otherwise consume a majority of the host processor's processing power and slow down overall system performance.
When used as coprocessors, Stratix IV FPGAs boost overall system performance by offloading complex computations in wireless, broadcast, medical imaging, and military systems from the host processor.
Altera offers a broad range of support services, tools, and development platforms for implementing DSP designs in Stratix IV FPGAs. You can also quickly develop Stratix IV FPGAs into user-defined FPGA coprocessors using DSP Builder, Altera's data-flow architecture development tool based on the industry-leading MATLAB and Simulink tools from The MathWorks.
Once the coprocessor architecture is captured, it can automatically be implemented into an Altera® Stratix IV FPGA or exported to Altera's SOPC Builder system development tool for further integration into the overall system architecture.
Altera also offers DSP development kits that you can use to verify your DSP systems in hardware in the prototype phase of your design cycle.
Platform Scalability
Stratix IV FPGAs support vertical package migration from small to large devices. This enables a single board design to scale from a small Stratix IV FPGA, like the EP4SGX70 device, to the industry’s highest performance 40-nm FPGA for DSP processing, the EP4SGX230 device. The EP4SGX230 device is capable of 700 giga multiply-accumulate operations per second (GMACS). This range of scalability is possible because of the parallel processing nature of the Stratix IV FPGA family. Table 2 illustrates the DSP performance capability of a small Stratix IV FPGA.
| Table 2. Stratix IV DSP Block Parallel Processing Performance |
| Specification |
Stratix IV EP4SGX230 |
| Total 18 x 18 Multipliers |
1,288 |
| Maximum Clock Frequency |
550 MHz |
| Maximum Performance |
1,288 multipliers at 550 MHz = 708 GMACS |
Stratix IV FPGAs are ideal for video and image processing, high-speed digital communications, and other high-performance DSP applications. Optimized DSP blocks in Altera's Stratix IV FPGAs combine with TriMatrix memory and adaptive logic modules (ALMs) to unleash the highest DSP performance in the industry.
At 700 GMACS, the DSP throughput of Stratix IV devices is orders of magnitude higher than any single-chip DSP processor available, easily meeting the requirements of the emerging standards and protocols shown in Table 3.
| Table 3. DSP Applications That Can Be Implemented Using Stratix IV DSP Blocks |
| Features |
Military Applications |
Image Processing |
Communications |
| Radar/Sonar |
Broadcast and Medical |
Wireless |
| Algorithms and Functions |
- Filtering
- Transforms
- Modulation
|
- Filtering
- Compression
- Scaling
|
- Chip-rate processing
- Equalization
- Digital IF (DDC, DUC)
|
| Standards and Protocols |
- |
|
- HSDPA, HSUPA
- MBMS, EDCH
- CDMA 2000, 1x EVDV
- OFDMA
- WiMAX (802.16d/e)
|
DSP Block Details
The Stratix IV DSP block is a high-performance silicon architecture with great programmability that delivers optimized processing across many applications. Each DSP block provides eight 18 x 18 multipliers, as well as registers, adders, subtractors, accumulators, and summation unit-functions that are frequently required in typical DSP algorithms. The DSP block supports completely variable bit-widths and various rounding and saturation modes to efficiently meet the exact requirements of your application. See Figure 1.
Figure 1. DSP Block Architecture
Table 4 shows the DSP resources of Stratix IV FPGAs.
| Table 4. Stratix IV FPGA DSP Resources |
| Stratix IV Family Variant |
Device |
Multipliers |
| 9 x 9 |
12 x 12 |
18 x 18 |
18 x 36 |
36 x 36 |
18 x 18
Complex |
Single Floating Point |
Double Floating Point |
|
Stratix IV GX
|
EP4SGX70
|
384
|
384
|
384
|
192
|
96
|
96
|
96
|
38
|
|
EP4SGX110
|
512
|
512
|
512
|
256
|
128
|
128
|
128
|
51
|
|
EP4SGX230
|
1,288
|
1,288
|
1,288
|
644
|
322
|
322
|
322
|
128
|
|
EP4SGX290
|
800
|
800
|
832
|
416
|
208
|
208
|
208
|
83
|
|
EP4SGX360
|
1,040
|
1,040
|
1,040
|
520
|
260
|
260
|
260
|
104
|
|
EP4SGX530
|
1,024
|
1,024
|
1,024
|
512
|
256
|
256
|
256
|
104
|
|
Stratix IV E
|
EP4SE110
|
512
|
512
|
512
|
256
|
128
|
128
|
128
|
51
|
|
EP4SE230
|
1,288
|
1,288
|
1,288
|
644
|
322
|
322
|
322
|
128
|
|
EP4SE290
|
800
|
800
|
800
|
400
|
200
|
200
|
200
|
80
|
|
EP4SE360
|
1,040
|
1,040
|
1,040
|
520
|
260
|
260
|
260
|
104
|
|
EP4SE530
|
1,024
|
1,024
|
1,024
|
512
|
256
|
256
|
256
|
102
|
|
EP4SE680
|
1,360
|
1,360
|
1,360
|
680
|
340
|
340
|
340
|
136
|
As with previous generation Stratix devices, Quartus® II software continues to deliver optimal mapping of your DSP algorithms to the Stratix IV ALM fabric, the TriMatrix memory, and the DSP blocks from HDL-specific and DSP-specific development tools and libraries.
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