At the 40-nm process, Stratix® IV FPGAs provide unmatched resources for integrating your next-generation, high-performance designs.
With 820K logic elements (LEs) and 23.1 Mbits of memory on a single FPGA, Stratix IV E FPGAs deliver the highest density and the fastest FPGA solutions for ASIC prototyping, and address partitioning and verification challenges.
With 530K LEs, 26.7 Mbits of memory, and 48 transceivers running up to 11.3 Gbps on a single FPGA, Stratix IV FPGAs deliver the most optimized high-speed serial interface solutions.
Stratix IV FPGAs are ideal for your high-end digital applications in ASIC prototyping and many other end markets, including wireline, wireless, military, and broadcast.
What Can You Achieve with an 820K Logic Element Stratix IV FPGA?
- Jumpstart your ASIC prototyping design by fitting up to 15 million ASIC gate designs in a single FPGA
- Simplify your prototyping board design by reducing the number of required FPGAs
- Accelerate your verification cycle through simpler partitioning and faster performance
- Leverage vertical migration to start prototyping today
- Rely on Hardcopy® ASICs to take your design to volume production faster and with less risk
- Reduce power consumption requirements through Programmable Power Technology
Table 1 shows the availability of the highest density Stratix IV FPGAs.
| Table 1. Availability of the Highest Density Stratix IV FPGAs | ||||||
| Stratix IV FPGAs | Logic Elements | Embedded Memory (Mbits) | DSP 18 x 18 |
I/O Pins |
Transceivers | Availability |
|---|---|---|---|---|---|---|
|
EP4SE820 |
820K |
23.1 |
960 |
1,120 |
0 |
April-2010 |
| EP4SE530 | 530K | 20.7 | 1,024 | 976 | 0 | Now |
| EP4S100G5 | 530K | 20.7 | 1,024 | 976 | 48 | Now |
| EP4SGX530 | 530K | 20.7 | 1,024 | 976 | 48 | Now |
Logic Efficiency
The core fabric of Stratix IV FPGAs is built from innovative logic units known as adaptive logic modules (ALMs). ALMs are extremely efficient in implementing logic because of their fracturability. For an equivalent sized part, Stratix IV FPGAs can implement more logic than the nearest competing device.
ALM fracturability allows two independent smaller functions to be implemented in one ALM, instead of partially filling two LEs and wasting the unutilized resources. Altera’s Quartus® II software automatically takes advantage of this and packs the design efficiently, minimizing under-utilized resources. This opens the door for fitting the design into smaller devices and reducing logic levels to increase fMAX.
