Stratix IV GX and HardCopy IV GX Transceiver Overview
Stratix® IV GX FPGAs and HardCopy® IV GX ASICs with embedded transceivers deliver breakthrough levels of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. The transceivers are based on 40-nm technology and include a number of features that ensure excellent jitter performance combined with superior signal integrity for both backplane and chip-to-chip applications. Building on the success of Stratix II GX transceivers, Stratix IV GX FPGA and HardCopy IV GX ASIC transceivers support emerging standards and proprietary serial protocols. The transceivers include several digital blocks that you can configure to simplify the implementation of these protocols.
Key Transceiver Features
- Up to 32 transceivers with clock data recovery (CDR), supporting data rates from 600 Mbps to 8.5 Gbps, plus up to an additional 16 transceivers with CDR, supporting data rates from 600 Mbps to 3.2 Gbps in Stratix IV GX FPGAs
- Up to 16 transceivers with CDR, supporting data rates from 600 Mbps to 6.5+ Gbps, plus up to an additional 8 transceivers with CDR, supporting data rates from 600 Mbps to 3.2 Gbps in HardCopy IV GX ASICs
- Dynamically programmable differential output voltage (VOD) and pre-emphasis settings for improved signal integrity
- User-controlled or adaptive 4-stage receiver equalization with up to 17dB of gain to compensate for frequency-dependent losses in the physical medium
- Support for CDR-based serial standards, including PCI Express, Serial RapidIO®, Gigabit Ethernet (GbE), XAUI/HiGig, the Optical Internetworking Forum (OIF) CEI-6G, Interlaken, SFI-5, GPON, SONET, CPRI, OBSAI, Fibre Channel, HyperTransportTM, SDI, and Altera’s SerialLite II
- Support for single-wide and double-wide basic modes to implement custom protocols
- Individual transmitter and receiver power-down to reduce power consumption during non-operation
- Selectable on-chip termination resistors for improved signal integrity on a variety of transmission media
- Programmable transceiver-to-FPGA interface supports 8-, 10-, 16-, 20-, 32-, and 40-bit-wide data transfer
- Receiver loss-of-signal indicator
- Built-in self test (BIST)
- Plug & Play Signal Integrity with hot insertion/removal protection circuitry
- Dynamic reconfiguration of the transceiver to support multiple protocols and data rates on the same channel without reprogramming the FPGA
- Each transmitter has two phase-locked loop (PLL) inputs and independent clock dividers to allow different clock rates for each channel
- Generic polarity inversion for basic modes and polarity inversion specifically for PCI Express
- Rate matcher, pattern detector, and word aligner with programmable patterns
- Dedicated circuitry compliant with the physical interface for PCI Express (PIPE), XAUI, and GbE
- PIPE interface connects directly to embedded PCI Express Gen1 (2.5 Gbps) and Gen2 (5.0 Gbps) hard IP or to soft IP
- Built-in byte ordering so that a frame or packet always starts in a known byte lane
- 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
- Receiver rate-matching FIFO buffer resynchronizes the received data with the local reference clock
- Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array
Block Diagram
Figure 1 shows the block diagram of the Stratix IV GX FPGA and HardCopy IV GX ASIC transceivers, both physical medium attachment (PMA) and physical coding sublayer (PCS). The blocks within the PCS can be bypassed, depending on the user’s requirements.
Figure 1. Stratix IV GX and HardCopy IV GX Transceivers, PMA, and PCS Block Diagram
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Stratix IV GX transceivers include dedicated circuitry to implement standard and proprietary protocols operating between 600 Mbps and 8.5 Gbps in native mode. HardCopy IV GX transceivers support 600 Mbps to 7 Gbps in native mode. The transceivers are also capable of supporting data rates as low as 270 Mbps using oversampling, which is important when supporting legacy protocols and protocols with multiple data rates. When augmented with Altera® intellectual property (IP), Stratix IV GX FPGA and HardCopy IV GX ASIC transceivers provide a complete, low-risk solution for serial protocol implementation.
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