Network-equipment designers require seamless communication among the chips in their system. Two common issues are mismatched protocols between components and implementation of custom functions in the data path. There are various specialized protocols for differing types of data-transfer topologies, such as backplanes or chip-to-chip communication. Stratix™ GX devices were built to bridge various high-speed communications protocols and to fully accommodate value-added custom functions. The following two bridging examples show the versatility of the Stratix GX transceiver block through its compatibility with standard and custom backplane interfaces. For more details on the Stratix GX transceiver block, visit the Stratix GX Transceiver page.
10 Gigabit Ethernet XAUI to SPI-4.2 Bridge
High-speed serial links that use the 10-gigabit attachment unit interface (XAUI) in backplane and chip-to-chip communication are growing rapidly. The chip-to-chip source-synchronous interface SPI-4.2 (also known as SPI-4 Phase 2 and POS-PHY Level 4) is also popular and is being used as a template for emerging interfaces such as Network Packet Switching Interface (NPSI).
Figure 1 shows a diagram of how Stratix GX devices can bridge communication between XAUI and SPI-4.2 while providing users with the ability to implement custom logic in the data path. In this example, four serial links running at 3.125 Gbps each are connected over a backplane to a Stratix GX device. Stratix GX devices are ideal for this type of application because they can support up to 20 serial links running at 3.125 Gbps. In addition, the Stratix GX programmable logic can be customized to implement traffic management, queue management, statistical metering, and control functions. Stratix GX device source-synchronous I/O blocks can then be used to implement the 16-bit LVDS SPI-4.2 interface with dynamic phase alignment (DPA).
For more details on the implementation of XAUI in Stratix GX devices, visit the Stratix GX Transceiver Protocols page.
For more detailed information on the implementation of SPI-4.2 with DPA in Stratix GX devices, visit the Stratix GX Source-Synchronous Protocols page.
Figure 1: Stratix GX Device in XAUI to SPI-4.2 Bridge Application
SONET/SDH Scrambled Backplane to SPI-4.2
Bridging a SONET/SDH scrambled backplane to an SPI-4.2 protocol is another sought-after solution needed in OC-192/STM-64 SONET/SDH systems. These systems typically transmit data across the backplane using scrambled coding techniques. Similar to the previous example using XAUI, Figure 2 shows a diagram of how Stratix GX devices can bridge communications between the backplane and SPI-4.2 and still allow for custom logic implementation in the data path. Stratix GX devices provide several key features to enable SONET/SDH backplane implementations, including the ability to bypass the 8B/10B, SERDES factors of 8 and 16 bits, and embedded A1A2 and A1A1A2A2 pattern detection.
For more details on the Stratix GX transceiver block, including support for scrambled coding schemes, visit the Stratix GX Transceiver page.
For more information on the implementation of SPI-4 in Stratix GX devices, visit the Stratix GX Source-Synchronous Protocols page.
Figure 2. Stratix GX Device in SONET Scrambled Backplane to SPI-4.2 Application
