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SerialLite for Stratix GX and Stratix II GX Devices

Home > Products > Devices > Stratix (and GX) > Stratix GX > Features > SerialLite for Stratix GX and Stratix II GX Devices

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The SerialLite protocol is designed as a lightweight, point-to-point protocol aimed at reducing footprint, latency, and overhead compared to other serial protocols. Because SerialLite focuses on providing essential functionality through scalability, this new, no-cost protocol serves as a complement to other serial protocols.

SerialLite is the first open-standard high-speed serial protocol with no restrictions on the implementation platform. The protocol specification and open-source reference design is now available.

SerialLite

Features

The protocol design includes a rich feature set and a single-lane transfer rate capability of 622 Mbps to 3.1875 Gbps (8B/10B encoded data). SerialLite currently has an aggregate data rate ranging from 500 Mbps to 40.8 Gbps. Future expansion of the platforms on which the protocol is offered will extend the aggregate data rate to be virtually unbounded.

The protocol incorporates the physical (PHY) layer and a portion of the link layer. The designer can augment the link layer further above SerialLite. The basic features of SerialLite include:

  • 8B/10B encoding is performed in the FPGA PHY layer
  • Packet encapsulation is performed in the link layer
  • Back-end interface uses the Atlanticâ„¢ interface that was pioneered by Altera

SerialLite is designed to be feature-scalable. Some of the optional features include:

  • Channel bonding scalability that is virtually unlimited
  • Capability to operate in streaming- or packet-based transfer mode
  • Packet prioritization
  • Data integrity protection using CRC-16 or CRC-32
  • Multiple channel multiplexing
  • Flow control
  • Retry-on-error

XAUI electrical specifications were used to define the SerialLite electrical specifications at the PHY layer. Due to the popularity of the XAUI specification, many designers are familiar with the XAUI protocol’s properties. The Stratix GX transceiver block was designed to meet XAUI specifications and therefore meets the SerialLite requirements.

Related Links

Cores
  • SerialLite Reference Design
Stratix GX
  • Stratix GX Device Family
  • Stratix GX Device Literature
Stratix II GX
  • Stratix II GX Device Family
Characterization Report
  • Stratix GX Characterization Report is available upon request; contact your local Altera Sales Office
Protocol Standard
  • SerialLite Protocol
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