Stratix® GX devices offer up to 45 receiver and 45 transmitter channels that support source-synchronous signaling for data transfer rates as high as 1 gigabit per second (Gbps). These source-synchronous channels provide a high-speed complementary solution to the high-bandwidth capabilities of the transceiver blocks in Stratix GX devices. Additionally, Stratix GX devices support the requirements of high-speed I/O protocols such as HyperTransportTM interfaces, RapidIO®, Network Packet Switching Interface (NPSI) (formerly known as CSIX) POS-PHY Level 4, SFI-4, and 10 Gigabit Ethernet XSBI. You can use Stratix GX devices to create a high-performance bridging function between devices that use different I/O protocols
As high-speed interfaces with source-synchronous clocking schemes approach 1 Gbps transfer rates, the margin for clock-to-channel and channel-to-channel skew contracts significantly. To stay within the permitted skew, you must use precise PCB design techniques because the slightest mismatch in trace lengths could result in erroneous data transfer. Other effects such as jitter, temperature, and voltage variations compound the problem, making simpler, static phase alignment techniques ineffective. Recognizing the challenges that engineers face when designing systems that transfer high-speed data, Altera incorporated dynamic phase alignment (DPA) circuitry in Stratix GX devices to dramatically simplify PCB design, eliminating the signal alignment problems introduced by skew-inducing effects.
Stratix GX DPA
The DPA circuitry eliminates clock-to-channel and clock-to-clock skew by aligning a sampling clock with the incoming data as shown in Figure 1.
Figure 1. Stratix GX Source-Synchronous Channels Support 1 Gbps
DPA uses the Stratix GX fast phase-locked loop (PLL) and is an optional feature of the dedicated source-synchronous circuitry. Using one of eight phase-shifted clocks generated by the fast PLL, the dynamic phase aligner samples the incoming data and aligns the data by choosing the clock phase that is closest to the center of the incoming data. This alignment is continuous and can compensate for dynamic changes in the real-time timing variations between the clock and data signals.
The DPA circuitry supports multiple serializer/deserializer (SERDES) factors including the 8x and 10x modes. Each channel has its own DPA circuit that provides independent data alignment for each channel; therefore, DPA can eliminate channel-to-channel skew as well as clock-to-channel skew, as shown in Figure 2.
Figure 2. Skew Correction with DPA Circuitry
Table 1 summarizes the DPA timing specifications in Stratix GX devices.
| Table 1. DPA Timing Specifications | |||
|---|---|---|---|
| Parameter | Value | ||
| Data Frequency Range | 415 megabits per second (Mbps) to 1 Gbps | ||
| Clock Frequency Range | 77.75 MHz to 644.53 MHz | ||
| Signaling Levels | LVDS, LVPECL, 3.3-V PCML, HyperTransport | ||
Differential I/O Standards
The Stratix GX source-synchronous circuitry supports the LVDS, LVPECL, 3.3-V PCML, and HyperTransport differential I/O standards. Use these standards for high-performance applications to create better noise margins, to provide lower electromagnetic interference (EMI), and for lower power consumption. Additionally, these standards support the high data throughput needed for high-speed interface standards such as HyperTransport interfaces, RapidIO, NPSI , POS-PHY Level 4 (SPI-4), SFI-4, 10 Gigabit Ethernet XSBI, and UTOPIA Level 4. Table 2 summarizes the differential I/O standards, maximum performance rates, and applications supported by Stratix GX devices.
| Table 2. Stratix GX Device Differential I/O Standard Performance | |||
|---|---|---|---|
| I/O Standard | Performance (Gbps) | Typical Application | |
| LVPECL | 1 | General-purpose | |
| 3.3-V PCML | 1 | Backplane | |
| LVDS | 1 | Backplane | |
| HyperTransport (1) | 1 | Host processor | |
Note:
1. HyperTransport protocol support limited to 1 Gbps.
