The SPI-4.2 protocol continues to gain broad industry acceptance as the standard interface for packet and cell transfers between physical layer (PHY) and link layer devices in multi-gigabit applications, including asynchronous transfer mode (ATM) and packet over SONET/SDH (STS-192/STM-64), 10 Gigabit Ethernet, and multi-channel Gigabit Ethernet.
Originally defined by the SATURN Development Group as POS-PHY Level 4 and subsequently adopted by the Optical Internetworking Forum (OIF), SPI-4.2 specifies a source-synchronous interface with differential data rates of at least 622 Mbps. Devices implementing SPI-4.2 are typically specified with rates of 700 to 800 Mbps, and in some cases, up to 1 Gbps. At these high data rates, it becomes more challenging to manage the skew between the clock and data signals. Also, it is quite common to design application-specific PHY cards for mid-plane interconnect to link layer devices across PCB connectors, as shown in Figure 1, reducing timing margin and increasing the challenge of managing channel skew.
Figure 1. Typical Application & Performance Requirements
The SPI-4.2 protocol specifies a training sequence which can be used by receivers to correct skew up to +/- 1 bit period. This function is commonly referred to as dynamic phase alignment (DPA). Stratix® GX devices are the first FPGAs with embedded DPA circuitry supporting data transfer rates as high as 1 Gbps. The SPI-4.2-compliant POS-PHY Level 4 MegaCore® function integrates this circuitry and offers a broad range of configuration options, allowing designers to customize the core to meet the specific requirements of their system.
Interoperability Testing
As a complex, high-speed interface to third-party devices, testing in hardware is essential to ensure interoperability. Altera works closely with other semiconductor vendors to complete testing, so our mutual customers are assured that our devices interoperate satisfactorily.
For more information on interoperability testing, refer to the following technical documentation:
- AN 228: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices (PDF)
- AN 227: SPI-4.2 Interoperability with the Intel® IXF1110 in Stratix GX Devices (PDF)
