Literature Licensing Buy On-Line Download Entire Site Part Number Knowledge DB

Home   |   Products   |   Support   |   End Markets   |   Technology Center   |   Education & Events   |   Corporate   |   Buy On-Line

Devices   |   Design Software   |   Intellectual Property   |   Design Services   |   Dev. Kits/Cables   |   Literature

High-End FPGAs       About Stratix Series    Stratix IV (E and GX)    Stratix III (L and E)    Stratix II (and GX)    Stratix (and GX)        Stratix        Stratix GX                Overview                Design Utilities                Features                Literature     Midrange FPGAs    Arria (GX)     Low-Cost FPGAs    Cyclone III    Cyclone II    Cyclone     CPLDs    MAX II (and G, Z)    MAX 3000A     ASICs       About HardCopy Series    HardCopy IV (E and GX)    HardCopy III    HardCopy II    HardCopy Stratix     Device-Specific Offerings    RoHS Compliant       Extended Temperature       Enhanced Temperature       Military Temperature     Configuration Devices    Enhanced Configuration    Serial Configuration     Mature Products       Product Listing

Home > Products > Devices > Stratix (and GX) > Stratix GX > Literature Print This Page Subscribe to Email Literature: Stratix GX Device Handbook The Stratix® GX Device Handbook is composed of three volumes. Volume 1 is the Stratix GX FPGA family data sheet. Volume 2 provides detailed information on the device features, including the transceiver. Volume 3 contains information on configuration, remote system upgrades, and Stratix GX board design guidelines. To view all three volumes, click the link below. Get more information on Stratix GX Pin-Outs. Check the Knowledge Database for Known Issues with the Stratix GX Handbook. Stratix GX Device Handbook (All Three Volumes) (21 MB) Volume 1 (ver 1.2, Jun 2006, 3 MB) Section I. Stratix GX Device Family Data Sheet (3 MB) Chapter 1. Introduction to the Stratix GX Device Data Sheet (ver 1.0, Feb 2005, 495 KB) Chapter 2. Stratix GX Transceivers (ver 1.1, Jun 2006, 349 KB) Chapter 3. Source-Synchronous Signaling with DPA (ver 1.1, Aug 2005, 216 KB) Chapter 4. Stratix GX Architecture (ver 1.0, Feb 2005, 1 MB) Chapter 5. Configuration & Testing (ver 1.0, Feb 2005, 499 KB) Chapter 6. DC & Switching Characteristics (ver 1.2, Jun 2006, 1 MB) Chapter 7. Reference & Ordering Information (ver 1.0, Feb 2005, 433 KB) Volume 2 (ver 2.0, Jun 2006, 10 MB) Section I. Stratix GX Transceiver User Guide (6 MB) Chapter 1. Introduction (ver 1.2, Jun 2006, 116 KB) Chapter 2. Stratix GX Analog Description (ver 1.2, Jun 2006, 553 KB) Chapter 3. Custom Mode (ver 1.2, Jun 2006, 950 KB) Chapter 4. SONET Mode (ver 1.2, Jun 2006, 800 KB) Chapter 5. XAUI Mode (ver 1.2, Jun 2006, 917 KB) Chapter 6. GIGE Mode (ver 1.2, Jun 2006, 787 KB) Chapter 7. Loopback Modes (ver 1.2, Jun 2006, 67 KB) Chapter 8. Stratix GX Built-In Self Test (BIST) (ver 1.1, Aug 2005, 2 MB) Chapter 9. Reset Control & Power Down (ver 1.0, Feb 2005, 662 KB) Chapter 10. Data & Control Codes (ver 1.0, Feb 2005, 486 KB) Chapter 11. Ports & Parameters (ver 1.1, Jun 2006, 137 KB) Chapter 12. REFCLKB Pin Constraints (ver 1.0, Feb 2005, 562 KB) Section II. Clock Management (1 MB) Chapter 13. General-Purpose PLLs in Stratix & Stratix GX Devices (ver 3.2, Jul 2005, 1 MB) Section III. Memory (518 KB) Chapter 14. TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices (ver 3.3, Jul 2005, 297 KB) Chapter 15. External Memory Interfaces in Stratix & Stratix GX Devices (ver 3.3, Jun 2006, 275 KB) Section IV. I/O Standards (870 KB) Chapter 16. Selectable I/O Standards in Stratix & Stratix GX Devices (ver 3.4, Jun 2006, 446 KB) Chapter 17. High-Speed Source-Synchronous Differential I/O Interfaces in Stratix GX Devices (ver 1.2, Jun 2006, 487 KB) Section V. Digital Signal Processing (940 KB) Chapter 18. DSP Blocks in Stratix & Stratix GX Devices (ver 2.2, Jul 2005, 255 KB) Chapter 19. Implementing High-Performance DSP Functions (ver 1.1, Sep 2004, 1 MB) Volume 3 (ver 1.2, Jun 2006, 5 MB) Section I. Configuration & Remote System Upgrades (1 MB) Chapter 1. Configuring Stratix & Stratix GX Devices (ver 3.2, Jul 2005, 546 KB) Chapter 2. Remote System Configuration with Stratix & Stratix GX Devices (ver 3.1, Sep 2004, 995 KB) Section II. Design Guidelines (3 MB) Chapter 3. Transitioning APEX Designs to Stratix & Stratix GX Devices (ver 3.0, Feb 2005, 280 KB) Chapter 4. Stratix GX Board Design Guidelines (ver 1.0, Feb 2005, 2 MB) Chapter 5. Quartus II Software Fitter Warnings (ver 1.0, Mar 2005, 137 KB) Related Documentation Data Sheets Stratix Series Device Thermal Resistance (ver 5.0, Oct 2008, 212 KB) Altera Device Package Information Data Sheet (ver 15.2, Sep 2008, 3 MB) Stratix GX Development Board Data Sheet (ver 1.1, Aug 2003, 544 KB) User Guides Double Data Rate I/O Megafunction User Guide (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) (ver 4.2, Jun 2007, 4 MB) altddio_DesignExample_ex1.zip ( 112 KB) altddio_DesignExample_ex2.zip ( 140 KB) altddio_ex1_msim.zip ( 18 KB) altddio_ex2_msim.zip ( 17 KB) PowerPlay Early Power Estimator User Guide for Stratix, Stratix GX & Cyclone FPGAs (ver 2.0, Oct 2005, 649 KB) Stratix GX Transceiver User Guide (ver 3.0, Jan 2005, 8 MB) Seriallite MegaCore Function User Guide (ver 1.0.0, Sep 2004, 942 KB) High-Speed Development Kit, Stratix GX Edition User Guide (ver 1.0, Aug 2003, 6 MB) Manuals Stratix II GX PCI Express Development Board Reference Manual (ver 1.0.1, Apr 2007, 2 MB) Application Notes AN 326: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices (ver 5.1, May 2008, 2 MB) AN 357: Error Detection & Recovery Using CRC in Altera FPGA Devices (ver 1.4, Jul 2008, 371 KB) AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 3.0, Jun 2008, 386 KB) AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices (ver 2.0, Dec 2005, 511 KB) Example 1: Shift Register in LEs ( 340 KB) Example 2: altpll_reconfig Design with the MIF ( 192 KB) Example 3: altpll_reconfig Design ( 192 KB) AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices (ver 2.0, Dec 2005, 428 KB) AN 325: Interfacing RLDRAM II with Stratix II, Stratix & Stratix GX Devices (ver 3.1, Nov 2005, 2 MB) AN 385: Using Stratix GX Transceivers for PCI Express (ver 1.0, Jun 2005, 4 MB) AN 382: Using Stratix GX Transceivers for CPRI (ver 1.0, May 2005, 953 KB) AN 360: Updating Simulation Models for the POS-PHY Level 4 MegaCore Function (ver 1.1, Dec 2004, 63 KB) AN 306: Implementing Multipliers in FPGA Devices (ver 3.0, Jul 2004, 733 KB) AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices (ver 1.0, May 2004, 280 KB) AN 227: SPI-4.2 Interoperability with the Intel IXF1110 in Stratix GX Devices (ver 1.0, May 2003, 456 KB) AN 228: SPI-4.2 Interoperability with PMC-Sierra XENON Family in Stratix GX Devices (ver 1.0, May 2003, 633 KB) AN 236: Using Source-Synchronous Signaling with DPA in Stratix GX Devices (ver 1.1, Jan 2003, 177 KB) White Papers Basic Principles of Signal Integrity (ver 1.3, Dec 2007, 548 KB) Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices (ver 1.1, May 2006, 319 KB) Compromises of Using a 10-Gbps Transceiver at Other Data Rates (ver 1.0, Jul 2005, 100 KB) Input Signal Edge Rate Guidance (ver 1.0, Jun 2005, 63 KB) Using Parity to Detect Memory Errors in Stratix Devices (ver 1.2, Feb 2005, 97 KB) Transient Voltage Protection for Stratix GX Devices (ver 1.0, Jan 2005, 283 KB) The Benefits of Altera’s High-Speed DDR SDRAM Memory Interface Solution (ver 1.1, May 2004, 358 KB) Implementing a Queue Manager in Traffic Management Systems (ver 1.1, Feb 2004, 125 KB) Altera Hot-Socketing & Power-Sequencing Advantages (ver 1.2, Feb 2004, 79 KB) Selecting the Correct High Speed Transceiver Solution (ver 1.0, Sep 2003, 2 MB) Using Pre-Emphasis and Equalization with Stratix GX (ver 1.0, Sep 2003, 2 MB) Traffic Management in Stratix GX Devices (ver 1.0, Dec 2002, 69 KB) Stratix GX in Storage Applications (ver 1.0, Nov 2002, 80 KB) Stratix GX in Switch Fabric Systems (ver 1.0, Nov 2002, 222 KB) The Evolution of High Speed Transceiver Technology (ver 1.0, Nov 2002, 438 KB) Selector Guides Stratix FPGA Series Package & I/O Matrix (ver 1.0, Aug 2006, 75 KB) Errata Sheets Stratix GX FPGA Errata Sheet (ver 1.6, Jul 2007, 179 KB) Product Overview Altera Enhanced COTS PLD Initiative (ver 1.1, Jul 2008, 122 KB) Rate This Page

Please Give Us Feedback

Home | Products | Support | End Markets | Technology Center | Education & Events | Corporate | Buy On-Line  Devices | Design Software | Intellectual Property | Design Services | Dev. Kits/Cables | Literature  Contact Us | Site Help | Site Map | Privacy | Legal Notice  Copyright © 1995-2008 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus and MegaCore are trademarks of Altera Corporation