Stratix GX Device Family Overview
Stratix® GX FPGAs give system architects a low-risk path to 3.125-Gbps transceiver applications. Based on Altera's Stratix architecture, Stratix GX devices fuse the industry's fastest FPGA architecture with high-performance multi-gigabit transceiver technology. With up to 20 full-duplex transceiver channels operating at up to 3.125 Gbps per channel, Stratix GX devices address high-speed backplane and chip-to-chip communication needs. In addition, Stratix GX devices have a very low power per quad transceiver block and feature embedded circuitry that provides 40" FR-4 backplane drive capability. Stratix GX devices also include:
- Dynamically programmable pre-emphasis
- Dynamically programmable receive equalization
- Dynamically programmable drive strength
- On-chip transmit & receive termination
Stratix GX devices offer source-synchronous differential signaling with dedicated dynamic phase alignment (DPA) circuitry operating at up to 1 Gbps. The Stratix GX programmable logic enables you to implement proprietary functionality in minimal time, achieve very high system performance, and differentiate products at very low risk.
Built on a 1.5-V, 0.13-µm, all-layer-copper SRAM process, Stratix GX devices are available in densities ranging from 10,570 to 41,250 logic elements (LEs) and have up to 3 Mbits of RAM. Stratix GX devices are capable of 1-Gbps source-synchronous differential I/O signaling, supporting the LVDS, LVPECL, 3.3-V PCML, and HyperTransport™ differential I/O electrical standards.
These devices support several high-speed protocols—including SerialLite, 10-Gigabit Ethernet (XAUI and XSBI), SONET/SDH, Gigabit Ethernet, 1G, 2G and 10-Gbps Fibre Channels, RapidIO™, Serial RapidIO, SFI-4, POS-PHY Level 4 (SPI-4 Phase 2), HyperTransport, PCI Express, HD-SDI, and UTOPIA IV standards. Stratix GX devices feature a complete clock management solution with hierarchical clock structure and up to eight phase-locked loops (PLLs). Stratix GX devices offer up to 14 digital signal processing (DSP) blocks with up to 112 9x9 embedded multipliers, optimized for complex applications that require high data throughput.
System designs that require a low-risk cost-reduction path for high-volume production can migrate Stratix GX designs seamlessly to mask-programmed, pin-compatible HardCopy® Stratix GX devices. Because HardCopy Stratix GX devices preserve the high-density, high-performance architecture of Stratix GX FPGAs, including the 3.125-Gbps high-speed transceivers, no additional high-speed board design engineering is required when migrating from Stratix GX FPGAs to HardCopy Stratix GX devices.
Table 1 outlines the Stratix GX device family members and features.
| Table 1. Stratix GX Device Overview |
| Feature |
EP1SGX10C |
EP1SGX10D |
EP1SGX25C |
EP1SGX25D |
EP1SGX25F |
EP1SGX40D |
EP1SGX40G |
| LEs |
10,570 |
0,570 |
25,660 |
25,660 |
25,660 |
41,250 |
41,250 |
| Full-Duplex Transceiver Channels |
4 |
8 |
4 |
8 |
16 |
8 |
20 |
Source-
Synchronous Channels |
22 |
22 |
39 |
39 |
39 |
45 |
45 |
| M512 RAM Blocks (512 bits + parity) |
94 |
94 |
224 |
224 |
224 |
384 |
384 |
| M4K RAM Blocks (4 Kbits + parity) |
60 |
60 |
138 |
138 |
138 |
183 |
183 |
| M-RAM Blocks (512 Kbits + parity) |
1 |
1 |
2 |
2 |
2 |
4 |
4 |
| Total RAM Bits |
920,448 |
920,448 |
1,944,576 |
1,944,576 |
1,944,576 |
3,423,744 |
3,423,744 |
| DSP Blocks |
6 |
6 |
10 |
10 |
10 |
14 |
14 |
| Embedded Multipliers (1) |
48 |
48 |
80 |
80 |
80 |
112 |
112 |
| PLLs (2) |
4 |
4 |
4 |
4 |
4 |
8 |
8 |
| Device Availability |
Buy Now |
Buy Now |
Buy Now |
Buy Now |
Buy Now |
Buy Now |
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Notes:
- Total number of 9×9 multipliers. To obtain the total number of 18×18 multipliers per device, divide the total number of 9×9 multipliers by a factor of 2. To obtain the total number of 36×36 multipliers per device, divide the total number of 9×9 multipliers by a factor of 8.
- Includes both enhanced PLLs and fast PLLs.
Table 2 shows an overview of Stratix GX device packaging and I/O pin counts.
| Table 2. Stratix GX Device Package & Maximum User I/O Pins |
Package Size
(mm x mm) |
EP1SGX10C |
EP1SGX10D |
EP1SGX25C |
EP1SGX25D |
EP1SGX25F |
EP1SGX40D |
EP1SGX40G |
672-Pin FineLine BGA®
27 x 27 |
330 |
330 |
426 |
426 |
- |
- |
- |
1,020-Pin FineLine BGA
33 x 33 (1) |
- |
- |
- |
542 |
542 |
548 |
548 |
Note:
- The total number of I/O pins for each package described above includes dedicated clock pins and dedicated fast I/O pins. However, it does not include the high-speed or clock reference pins for high-speed I/O capability.
Table 3 shows the appropriate configuration devices to use for Stratix GX devices.
| Table 3. Appropriate Configuration Devices for Stratix GX FPGAs |
Configuration
Device |
Number of Devices |
| EP1SGX10C |
EP1SGX10D |
EP1SGX25C |
EP1SGX25D |
EP1SGX25F |
EP1SGX40D |
EP1SGX40G |
| EPC2 |
3 |
3 |
5 |
5 |
5 |
8 |
8 |
| EPC4 |
1 |
1 |
N/A |
N/A |
N/A |
N/A |
N/A |
| EPC8 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| EPC16 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
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