High-Performance Stratix Architecture
The high-performance Stratix™ device architecture consists of vertically arranged logic elements (LEs), TriMatrix™ memory blocks, digital signal processing (DSP) blocks, and phase-locked loops (PLLs) that are surrounded by I/O elements (IOEs) as depicted in Figure 1. A speed-optimized interconnect and low-skew clock network provide connectivity between each of these structures for clock and data signals.
Figure 1: Stratix Device Architecture
Maximized Interconnect Performance
Stratix devices are based on the MultiTrack™ interconnect with DirectDrive™ technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths used for communication within and between distinct design blocks. DirectDrive technology is a proprietary, deterministic routing technology that ensures identical routing resource usage for any function, regardless of its placement within the device, as illustrated in Figure 2. This technology greatly simplifies the system integration stage of block-based designs by eliminating the often time-consuming system re-optimization process that typically follows design changes and additions.
Figure 2: Direct Drive Technology Preserves Performance
These two new architectural advances give designers the technology to freely add, modify, and move various portions of their design without negatively affecting design performance.
Clock Networks for Many Needs
The MultiTrack interconnect structure is complemented by an advanced, low-skew clock network for clock distribution within the device, providing access to up to 22 clock domains per region. Each Stratix device features up to 16 global clock networks that span the entire device, feeding all architectural structures. Global clocks can be driven by internal logic, phase-locked loop (PLL) outputs, or device input pins, and can be used for other device-wide signals with large fan-outs such as asynchronous clears and clock enables, as shown in Figure 3.
Figure 3: Clock Distribution in Stratix Devices
Additionally, each device quadrant has four regional clock networks that can be driven by internal logic, PLL outputs, or device input pins. These clock networks are ideal for localized functions because they provide the shortest paths with the least amount of skew within the quadrant.
Fast regional clock networks are provided for high fan-out signals within a quadrant or half-quadrant in larger devices. These clock networks are driven by separate input pins or can be driven by signals from the peripheral I/O bus.
This architecture results in up to 40 unique clock networks per device, where any node can be driven by up to 22 independent clocks.
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