DDR SDRAM—Memory Solutions Center
To keep up with the growing industry needs, memory designers are migrating from single data rate (SDR) SDRAM memory to double-data rate (DDR) SDRAM memory. In DDR memories, data is clocked both on the rising edge and on the falling edge of the clock, effectively doubling the raw bandwidth over SDR. Today, DDR memories are widely used in computers, servers, storage, and networking and communication equipment. They are becoming the de-facto standard for all designers who wish to integrate large amounts of low-cost memory into their designs.
Altera provides a complete system solution to help system designers successfully interface Altera® FPGAs to DDR memories. The complete solution includes technical documentation, software and tool support, intellectual property (IP) cores, demonstration boards, and simulation models. Table 1 lists the DDR SDRAM memory interface supported by Altera FPGAs.
| Table 1. DDR SDRAM memory interface supported by Altera FPGAs |
| Device |
DDR SDRAM Interface Performance |
| Stratix™ |
400 Mbps (200 MHz) |
| Stratix GX |
400 Mbps (200 MHz) |
| Cyclone™ |
266 Mbps (133 MHz) |
Technical Documentation
Altera offers a comprehensive list of technical documentation, including complete information about each device and detailed documentation to help design DDR memory interfaces. Table 2 lists the available technical documentation and their correlated devices.
Software Support & Tools
Altera offers software support and tools that aid in the DDR SDRAM memory interface design process.
| Table 3. Software Support & Tools |
| Feature |
Applicable Devices |
Round Trip Delay Calculator & User Guide
(Contact Altera or local Altera FAE) |
Stratix
Cyclone |
| IBIS Models for Stratix I/O Buffers |
Stratix |
SPICE Models for Stratix I/O Buffers
(Contact Altera or local Altera FAE) |
Stratix |
SPICE Models for Stratix GX I/O Buffers
(Contact Altera or local Altera FAE) |
Stratix GX |
Round trip delay calculator and user guide
(Contact Altera or local Altera FAE) |
Stratix
Stratix GX |
| ALTDQS Megafunction — Instantiates the DQS phase shift circuitry (available in the Quartus® II software) |
Stratix
Stratix GX |
IP Cores & Reference Designs
Altera offers fully-customizable IP megafunction DDR SDRAM controller cores developed and tested by Altera and Altera Megafunction Partners Program (AMPPSM) partners, available at the IP MegaStore™ web site. These megafunctions allow designers to quickly and easily incorporate the latest semiconductor memory technologies into their FPGA designs using an intuitive graphical user interface (GUI) from within the Quartus II software. Using off-the-shelf IP cores minimizes the time spent designing the basic building blocks of any system and allows the designer to concentrate on the core functionality of the system. Table 4 lists DDR SDRAM IP cores and reference designs built by Altera and AMPP Partners.
Note:
- MMAV = Memory models, advanced verification
- MMAV is a memory modeler for board level simulation between Altera FPGA and external memory
- Denali has simulation models for over 4,000 memory components for SRAM, DRAM and Flash
- Denali has made exclusive arrangement for Altera customers to receive a free MMAV evaluation kit and promotional pricing for the retail version. More information on the Denali-Altera partnership is available on the Denali website
- PureView Memory Modeler AV User's Guide (PDF) has information on how to use Denali models for memory interface design verification.
Demonstration Boards
Altera offers demo boards that enable memory designers to implement and test DDR SDRAM memory interfaces. Table 5 lists the demonstration boards available for DDR memory interfaces.
| Table 5. Demonstration Boards Available for DDR Memory Interfaces |
| Demonstration Board Name |
Contact Information |
| Stratix Demonstration Board with 400 Mbps DIMM Support |
Contact Altera or local Altera FAE |
Presentations & Articles
Table 6 contains links to presentations and articles on Altera’s DDR SDRAM memory interface solution.
Related Links
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Literature
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