Differential & Single-Ended I/O Standards in Stratix Devices
Stratix™ devices support a variety of differential and single-ended I/O standards, and easily interface with backplanes, host processors, buses, memory devices, and 3D graphics controllers. The Stratix device family offers designers up to 116 high-speed differential I/O channels with up to 80 channels optimized for 840 Mbps operation. Each of these I/O channels includes dedicated serializer/deserializer (SERDES) circuitry to facilitate easy implementation of high-speed interface standards such as POS-PHY Level 4 (SPI-4 Phase 2), SFI-4, FlexBus Level 4, HyperTransport™, RapidIO, 10-Gigabit Ethernet (XSBI), and UTOPIA Level 4 as shown in Table 1. Support for high-speed I/O interfaces and high-bandwidth protocols makes Stratix devices an ideal bridging solution that can be used to interface with all parts of a system.
| Table 1. Stratix I/O Standard Support |
| Feature |
Single-Ended I/O Standards |
Differential I/O Standards |
External Memory Interfaces |
| Electrical Standards |
LVTTL
LVCMOS
SSTL
HSTL
GTL+
CTT
AGP |
LVDS
LVPECL
PCML
HyperTransport |
SSTL-2,
SSTL-3,
SSTL-18
HSTL Class I & II
Differential SSTL
Differential HSTL |
| Dedicated Circuitry |
Terminator™ Technology
- Series Termination
- Parallel Termination
PCI Clamp Diode |
True-LVDS™ Circuitry
- Dedicated SERDES Circuitry
- Differential I/O Buffers
- Data Realignment |
Dedicated DDR Circuitry
- Dedicated DQS Circuitry
- DDR Timing Circuitry
- Multiple I/O Registers |
| Related Intellectual Property (IP) Cores & Reference Designs |
PCI-X
32-/64-Bit PCI
CSIX
DMA Controller |
POS-PHY Level 4 (SPI-4 Phase2)
Flexbus Level 4
HyperTransport
RapidIO
10-Gigabit Ethernet (XSBI)
Utopia Level 4 |
DDR SDRAM Controller
SDR SDRAM Controller
DDR FCRAM Controller
QDR SRAM Controller
ZBT SRAM Controller |
Using Dedicated Circuitry to Meet High-Performance Specifications
Stratix devices feature dedicated circuitry to meet the stringent timing requirements imposed by high-speed interface standards to achieve high performance. The True-LVDS™ feature in Stratix devices offers SERDES circuitry, differential I/O buffers, data realignment circuitry and phase-locked loops PLLs for fast, accurate data transfer. The data realignment circuit adjacent to the high-speed I/O buffers aligns the data's byte boundary on each channel. The data realignment feature can provide convenient data synchronization between different channels as well as between different devices interfacing with a single Stratix device. On-chip PLLs offer multiple clock domains on each I/O bank, providing clocking flexibility for meeting stringent timing specifications such as TCCS, RSKM, and SW parameters. The PLLs can also accept input clock signals with frequencies up to 645 MHz, which enable support for high-speed interface standards such as SFI-4 and XSBI. For more information, refer to Using High-Speed Differential I/O Interfaces in Stratix Devices chapter of the Stratix Device Handbook.
Differential I/O Standards
Stratix devices offer the True-LVDS feature to support the LVDS, LVPECL, PCML, and HyperTransport differential I/O standards. These differential I/O standards are more commonly used due to their higher performance, better noise margins, lower electromagnetic interference (EMI), and lower power consumption. In addition, these differential I/O standards support the high data throughput necessary for high-speed interface standards such as POS-PHY Level 4 (SPI-4), SFI-4, XSBI, UTOPIA Level 4, and RapidIO. Table 2 summarizes the differential I/O standards, performance targets and applications supported in Stratix devices.
| Table 2. Stratix Device Differential I/O Standard Performance |
| I/O Standard |
Performance Target |
Typical Application |
| LVPECL |
840 Mbps |
General Purpose |
| PCML |
840 Mbps |
Backplane |
| LVDS |
840 Mbps |
Backplane |
| HyperTransport |
800 Mbps |
Host Processor |
| Differential HSTL |
200 MHz |
Memory |
| Differential SSTL |
200 MHz |
Memory |
Note to Table 2:
-
These I/O standards are applicable to clock signals only
Single-Ended I/O Standards
Stratix devices support single-ended I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, GTL, GTL+, PCI-X, AGP, and CTT to interface with other devices on a board. Single-ended systems provide more current drive capacity than differential I/O standards, and they are critical when working with advanced memory devices such as DDR SDRAM and ZBT SRAM devices. Table 3 lists the single-ended I/O standards supported in Stratix devices.
| Table 3. Stratix Device Single-Ended I/O Standard Support |
| I/O Standard |
Performance Target |
Typical Application |
| 3.3-V/2.5-V/1.8-V LVTTL |
250 MHz |
General Purpose |
| 3.3-V/2.5-V/1.8-V/1.5-V LVCMOS |
250 MHz |
General Purpose |
| 3.3-V/2.5-V GTL |
100 MHz |
Backplane |
| 3.3-V/2.5-V GTL+ |
200 MHz |
Backplane |
| SSTL-3 Class I & II |
166 MHz |
SDRAM |
| SSTL-2 Class I & II |
200 MHz |
DDR I SDRAM |
| SSTL-18 Class I & II |
200 MHz |
DDR II SDRAM |
| 1.5-V HSTL I & II |
250 MHz |
Memory & Switch Fabric |
| 3.3-V PCI |
66 MHz |
PC & Embedded |
| 3.3-V PCI-X |
133 MHz |
PC & Embedded |
| Compact PCI |
66 MHz |
PC & Embedded |
| 3.3-V/1.5-V 1x AGP |
66 MHz |
3-D Graphics |
| 3.3-V/1.5-V 2x AGP |
133 MHz |
3-D Graphics |
| CTT |
250 MHz |
Backplane |
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