| Table 1. Stratix Features at a Glance |
| Feature |
Description |
| High-Performance Architecture |
| High-Performance Architecture |
The high-performance Stratix device architecture consists of a speed-optimized interconnect and a highly efficient clock network that provide connectivity between logic elements (LEs), TriMatrix memory blocks, digital signal processing (DSP) blocks, phase-locked loops (PLLs), and I/O elements (IOEs) to maximize system performance. Designers requiring higher performance can use Stratix II FPGAs. |
| Up to 79,040 LEs & up to 7 Mbits of Embedded Memory |
The high device density of Stratix FPGAs and embedded memory complement the bandwidth and performance of the Stratix device architecture. Designers requiring higher density can use Stratix II FPGAs . |
| High Memory Bandwidth and High-Speed External Memory Interfaces |
| TriMatrix Memory |
TriMatrix memory offers up to 7 Mbits of RAM and 8 terabits per second of device memory bandwidth. This complex memory structure includes three sizes of embedded RAM blocks—M512, M4K, and M-RAM blocks—that can be configured to support a wide range of applications. |
| External Memory Interfaces |
Stratix FPGAs provide advanced external memory interfaces, allowing designers to integrate external high-density SRAM and DRAM devices into complex system designs without degrading data access performance. |
| SRAM Devices |
Stratix FPGAs support interfaces with three types of SRAM devices—double data rate (DDR), quad data rate (QDR), QDRII, and zero bus turnaround (ZBT)—at up to 200 MHz. |
| DRAM Devices |
Stratix FPGAs support interfaces with three types of high-speed synchronous DRAM (SDRAM) devices: single data rate (SDR SDRAM), DDR SDRAM, and fast-cycle (FCRAM) with up to a 200-MHz clock. |
| High-Performance Digital Signal Processing (DSP) |
| DSP Blocks |
Stratix FPGAs include high-performance embedded DSP units that are optimized for DSP applications. The DSP blocks eliminate performance bottlenecks in DSP applications, provide predictable and reliable performance, and result in resource savings without compromising performance. |
| DSP Performance |
Stratix FPGAs offer higher data processing capacity than DSP processors for maximum system performance. |
| Soft Multipliers |
Stratix FPGAs provide a flexible implementation of soft multipliers that can be configured for different data width and latency. The soft multipliers provide very high DSP throughput in addition to the DSP blocks. |
| High I/O Bandwidth and High-Speed Interfaces |
| High I/O Bandwidth |
With support for a variety of single-ended and differential I/O standards, Stratix devices easily interface with backplanes, host processors, buses, memory devices, and 3D graphics controllers. |
| Differential I/O Support |
The Stratix True-LVDS circuitry offers up to 152 high-speed differential I/O channels with up to 80 channels optimized for data rates up to 840 Mbps. It also addresses the high-performance needs of emerging I/O interfaces, including support for the LVDS, LVPECL, PCML, and HyperTransport™ standards. |
| Single-Ended I/O Support |
Stratix FPGAs support high-bandwidth single-ended I/O interface standards, such as SSTL, HSTL, GTL, GTL+, CTT, and PCI-X, needed for today's demanding system requirements. |
| High-Speed Interfaces |
Stratix FPGAs support a wide array of high-speed interface standards, such as the SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, HyperTransport, RapidIO®, and UTOPIA IV standards, for flexibility and fast time-to-market. |
| System Clock Management |
| Clock Management Circuitry |
Stratix FPGAs feature up to 12 programmable PLLs and 40 system clocks, providing robust clock management and frequency synthesis capabilities for maximum system performance. |
| Clock Management Features |
Stratix PLLs offer features previously found only in high-end discrete PLL devices, including clock switchover, PLL reconfiguration, spread-spectrum clocking, frequency synthesis, programmable phase shift, programmable delay shift, external feedback, and programmable bandwidth. These features allow designers to manage system timing on and off the Stratix FPGA. |
| Automatic Cyclic Redundancy Code (CRC) Checking |
| CRC |
Stratix FPGAs feature automatic 32-bit CRC checking. A single click in Quartus® II version 4.1 software simplifies setup and activates the device's built-in CRC checker. It is the most cost-effective FPGA solution available for single event upset (SEU). |
| On-Chip Hot-Socketing and Power-Sequencing Support |
| Hot Socketing & Power Sequencing |
Stratix FPGAs offer robust on-chip hot-socketing and power-sequencing support that ensures proper device operation independent of the power-up sequence. This feature also protects the device and tri-states I/O buffers before and during power up, making Stratix FPGAs ideal for multi-voltage systems as well as for applications that require high availability and redundancy. |
| Remote System Upgrade Capabilities |
| Remote System Upgrades |
Stratix FPGAs feature a remote system upgrade capability, allowing secure, reliable, error-free deployment of system upgrades from a remote location. |
| Embedded Processor Cores |
| Nios II Family of Embedded Processors |
The advanced architectural features of Stratix FPGAs combined with Nios® II embedded processors offer unparalleled processing power to meet the needs of networks, telecommunications, DSP applications, mass storage, and other high-bandwidth systems. Stratix FPGAs improve the performance of Nios II processors to over 150 DMIPS. |
| Low-Cost Volume Production Devices |
| HardCopy Stratix ASICs |
HardCopy® Stratix ASICs offer a low-cost seamless migration path to volume production for Stratix designs. In addition, the mask-programmed HardCopy Stratix devices can provide faster performance (an average of 50 percent increase) than the fastest Stratix FPGA speed grades. For the highest performance, Stratix II FPGAs are supported by HardCopy II ASICs. |
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