Stratix™ devices support a wide array of high-speed interface standards for flexibility and fast time-to-market, including the 10-Gigabit Ethernet (XSBI), SFI-4, POS-PHY Level 4 (SPI-4 Phase 2), HyperTransport™, RapidIO™, and UTOPIA IV standards (as shown in Figure 1 and Table 1).
Designers can use Altera® intellectual property (IP) cores to bridge between high-speed interfaces using the Atlantic™ local interface. In addition, Stratix devices can support up to four high-bandwidth interfaces in one device for an unparalleled bridging solution.
Figure 1: Stratix Support for Various High-Speed Interfaces
| Table 1: Standard Interfaces Supported in Stratix | ||||||
|---|---|---|---|---|---|---|
| Feature | 10-Gigabit Ethernet XSBI | SFI-4 | POS-PHY Level 4 (SPI-4 Phase 2) |
HyperTransport | RapidIO | UTOPIA IV |
| Maximum Bandwidth (Gbps) | 10 | 10 | 10 | 6.4 | 10 | 10 |
| Data (Bus Width) | 16 | 16 | 16 | 8, 16, 32 | 8, 16 | 8, 16, 32 |
| Clocks | 1 | 1 | 1 | 1, 2, 4 | 1, 2 | 1 |
| Maximum Data Rate (Mbps) | 644.53 | 622.08 | 840 | 800 | 500 | 415 |
| Maximum Clock Rate (MHz) | 644 | 622 | 420 | 400 | 250 | 415 |
| Electrical Standard | LVDS | LVDS | LVDS | HyperTransport | LVDS | LVDS |
10-Gigabit Ethernet (XSBI)
The 10-gigabit Ethernet XSBI interface is a 16-bit LVDS interface used to connect the physical coding sublayer (PCS) and physical medium attachment (PMA) sublayers that are common to a family of 10-Gbps physical layer implementations, collectively known as 10GBASE-R. XSBI is based on the Optical Internetworking Forum (OIF) standard SFI-4. Stratix devices support the required data rates of up to 644.53 Mbps along with the 1:1 relationship required between clock frequency and data rate. The Stratix differential I/O phase-locked loop (PLL) was designed to support the high clock frequencies and 1:1 relationship needed for interfaces such as XSBI and SFI-4. XGMII is another 10 Gigabit Ethernet interface standard that is supported in Stratix devices through the use of the HSTL I/O standard.
SFI-4
SFI-4 is an OIF standard used in an OC-192 SONET system to link the framer and the serializer/deserializer (SERDES). Similarly to XSBI, Stratix devices support the required data rates of up to 622.08 Mbps along with the 1:1 relationship required between clock frequency and data rate. For interfaces such as SFI-4 and XSBI that require this 1:1 relationship, the Stratix differential I/O PLL was designed to support high clock frequencies. Support for SFI-4 extends the reach of high-density programmable logic from the backplane to the physical layer devices.
POS-PHY Level 4 (SPI-4 Phase 2)
POS-PHY Level 4 interfaces cell and packet transfers between physical (PHY) and link layer devices. POS-PHY Level 4 enables 10-Gbps data transfer and is primarily used in OC-192 systems. Along with the Stratix family's advanced differential I/O capabilities, other features such as TriMatrix™ memory, advanced PLL technology, and double data rate (DDR) I/O capabilities combine to deliver a 840-Mbps POS-PHY Level 4 solution.
HyperTransport
HyperTransport technology is a high-speed, high-performance, point-to-point link technology primarily used as a processor interface. Stratix differential I/O buffers have been designed to support the specific requirements of the physical layer of HyperTransport technology, including the requirements for a center-aligned clock (with respect to the transferred data) and DDR I/O buffers.
RapidIO
The RapidIO interconnect architecture was designed to link network processors, digital signal processing (DSP) devices, and other peripheral devices. RapidIO is a high-performance, packet-switched interconnect technology that can exceed 10-Gbps throughput through the use of LVDS links. Stratix devices support the 250-MHz clock frequency and 500-Mbps data rate through the DDR I/O capabilities. With TriMatrix memory—the Stratix family's leading-edge embedded memory resource—implementing the buffering requirements for a RapidIO system in Stratix devices is easy.
