System Tests between Stratix FPGA & Micron DDR SDRAM DIMM
Altera’s Stratix™ and Stratix GX devices are hardware-verified to interface with double data rate (DDR) SDRAM memory at speeds over 400 Megabits per second (Mbps) (200 MHz). This web page provides a summary of system-level DDR SDRAM interface tests performed between Stratix FPGA and Micron’s 184-pin, non-buffered, dual in-line memory module (DIMM).
Highlights from the system tests include:
- System performance exceed 400 Mbps under worst-case conditions (low voltage, high temperature, read-all write-all configuration, a noisy signal path that includes Mictor connectors and a device socket)
- System performance under typical (nominal voltage and temperature) operating conditions is approximately 440 Mbps
- Test waveforms correlate very well with simulation waveforms
Experiment Setup
Table 1 lists the test conditions for Stratix and Micron DDR SDRAM testing.
| Table 1. Experiment Setup for Stratix DDR SDRAM Interface Testing |
| Test Setup Parameter |
Description |
| Memory Specifications |
Micron 184-pin DIMM, Part # MT16VDDT3264AG-403B |
| DDR SDRAM Controller |
Altera® DDR SDRAM Controller IP |
| Stratix Device |
EP1S25F780C5 |
| Voltage |
Worst-case, nominal and best-case conditions (1) |
| Temperature |
Worst-case, nominal and best-case conditions (1) |
Notes to Table 1:
- Worst-case: High temperature (85°C) and low voltage (nominal VCC – 5%)
Nominal case: Room temperature and nominal VCC
Best-case: Low Temperature (0°C) and high voltage (nominal VCC + 5%)
Figures 1 and 2 show the board setup for Stratix DDR SDRAM experiments. The Stratix EP1S25F780C5 device is placed in a socket at the back of the mother board. The daughter board contains four 184-pin DIMM sockets and is connected to the mother board via Mictor connectors.
Figure 1. Board Setup for Stratix/DDR SDRAM Experiments, Top View
Figure 2. Bottom View of the Daughter Board
Design File
Figure 3 shows a block diagram of the design used to verify interoperability between Stratix FPGAs and Micron DDR DIMM.
The DDR controller intellectual property (IP) block consists of the Altera DDR SDRAM Controller MegaCore® function. Customers can download the free version to evaluate this controller.
The linear feedback shift register (LFSR) write data generator block generates random data to be written to the memory.
The user logic verifies if the read-data is the same as the write-data. The match flag of the comparator is connected to an output pin and is monitored on the Lecroy scope. When both the inputs to the comparator are the same, the match flag switches to logic level high.
Figure 3. Block Diagram
Experiment Results
System Performance Measurements
The table below lists the fMAX results from system performance measurements when a PRBS-8 pattern was transmitted and received.
|
Table 2. System Performance Measurements |
|
Ambient Temp (1) |
VCC (1) |
Write-All, Read-All
fMAX (Mbps) |
Write-Read
fMAX (Mbps) |
|
70° C |
Nom – 5% (2) |
410.8 |
413.2 |
|
Nom (2) |
413.6 |
419.4 |
|
Nom + 5% (2) |
419.2 |
426.4 |
|
25° C |
Nom – 5% (2) |
425.2 |
430.8 |
|
Nom (2) |
434.2 |
440.6 |
|
Nom + 5% (2) |
437.4 |
443.8 |
|
0° C |
Nom – 5% (2) |
433.2 |
437.6 |
|
Nom (2) |
435 |
444.2 |
|
Nom + 5% (2) |
438.6 |
450.2 |
Notes:
- Voltage and temperature variations apply to both the DDR DIMM and Stratix device
- Voltage
- Nom – 5%: VCC = 1.425V, VDD = 2.55V
- Nom: VCC = 1.5V, VDD = 2.65V
- Nom + 5%: VCC = 1.575V, VDD = 2.75V
Summary of System Performance Test Results
Following is the summary of the systems tests between the Stratix FPGA and Micron DDR SDRAM DIMM.
- System performance exceed 400 Mbps under worst-case conditions (low voltage, high temperature, read-all write-all configuration, a noisy signal path that includes Mictor connectors and a device socket)
- System performance under typical operating conditions is approximately 440 Mbps
Correlation with Simulation
Test results were compared with simulation results to check for correlation between simulation and silicon measurements. Figure 4 compares simulation waveform with measured waveform for the DQ and DQS signals in a “write” transaction. The scale on both the waveforms is the same. Simulation waveform and actual waveform from hardware tests correlate very well.
Figure 4. Simulation Waveform Compared with Measured Waveform for the DQ & DQS Signals in a “Write” Transaction
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