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DSP Performance in Stratix Devices

Stratix™ devices, which feature dedicated digital signal processing (DSP) block circuitry are displacing traditional DSP hardware alternatives (such as DSP processors) because Stratix DSP blocks offer higher data processing capacity and are more flexible and cost-effective than discrete DSP processors. DSP processors typically have up to 8 dedicated multipliers, whereas Stratix devices offer up to 176 dedicated multipliers as well as any additional logic element-based multipliers needed. The logic element-based implementation in Stratix devices provides tremendous flexibility and ease-of-design.

Stratix devices are the ideal choice for implementing algorithms that greatly benefit from the large number of multipliers in Stratix devices, including finite impulse response (FIR) filters, forward error correction (FEC), modulation-demodulation, and encryption.

Further, with the availability of software tools such as the Altera® DSP Builder (an interface between the Quartus® II software and the MATLAB/Simulink tool), Stratix devices can be used to implement entire DSP systems such as rake receivers and W-CDMA transmitters. DSP Builder combines the algorithm development, simulation, and verification capabilities of MathWorks' MATLAB and Simulink system-level design tools with the HDL synthesis, simulation, and verification capabilities of Altera Quartus II development software, making DSP designs much easier for Stratix devices.

Higher Data Throughput

Each DSP block in Stratix devices offers up to 8 parallel multipliers that can run at 300 MHz and provide data throughput of 2.4 giga multiply-accumulates per second (GMACS) per DSP block. The largest Stratix device, the EP1S80 device, offers 22 DSP blocks that can perform up to 176 parallel multiplications and provide a combined data throughput of 52.8 GMACS. Traditional DSP processors can perform only up to 8 parallel multiplications and can provide only up to 8.8 GMACS. As shown in Figure 1, given this increased processing capability, Stratix devices can replace DSP processors in a high-performance communication system.

Figure 1. Stratix Device in a Communications Transceiver System

Figure 1. Stratix Device in a Communications Transceiver System

Using LEs to Implement Multipliers

In addition to the dedicated multipliers inside the DSP blocks, multipliers and DSP functions can be implemented in Stratix logic elements (LEs). For example, a 256-tap FIR filter can be implemented using about 10,000 LEs in a Stratix device. The largest Stratix device, the EP1S80, which has 79,040 LEs, can accommodate 8 such filters. Each filter would run at 200 MHz, which implies an overall device throughput of 410 GMACS arising from the LE-based implementation. When combined with the 52.8-GMACS throughput from its DSP blocks, Stratix devices can offer up to 463 GMACS of data throughput.

Resource Savings Using High Performance DSP Blocks & TDM

The high-performance multipliers in DSP blocks and on-chip phase-locked loops (PLLs) available in Stratix devices can save logic resource utilization for multi-channel applications where each channel is running at a relatively low speed. If the on-chip multipliers are made to run at a much higher frequency than is needed for the application, then the same set of multipliers can be shared between different channels using the time domain multiplexing (TDM) concept as shown in Figure 2a and 2b.

Figure 2a. Single Channel Operates at 10 Msps

Figure 2a. Single Channel Operates at 10 Msps

Figure 2b. Stratix DSP Blocks Operating at 250 Msps Can Accommodate 25 Channels with TDM & PLLs

Figure 2b. Stratix DSP Blocks Operating at 250 Msps Can Accommodate 25 Channels with TDM & PLLs

This TDM-based implementation provides tremendous resource savings. For example: implementing 25 channels of 144-Tap FIR filter without using DSP Blocks and TDM concept would consume 173,000 LEs. On the other hand, using the DSP blocks and TDM concept, the same 25 channels of 144-Tap FIR filter can be implemented in 16 DSP Blocks, 5000 LEs and 38 Kbits of memory. The TDM-based implementation provides 97% lesser LE utilization.

Stratix devices provide higher performance and are more efficient, flexible, and cost-effective than DSP processors. It offers the best alternative for system design needs while implementing DSP systems such as:

  • Third-generation (3G) wireless base stations
  • Multimedia applications
  • Voice over Internet protocol (VoIP)
  • Image-processing applications

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