On-Chip Termination Questions & Answers
With the increasing system speeds and clock edge rates, signal integrity has become crucial in digital designs. To improve signal integrity, both single-ended and differential signals should be properly terminated. Termination can be implemented with external termination resistors or with on-chip termination technology. Termination with external resistors offers better resolution and is recommended for designs with stringent tolerance requirements.
The most frequently asked questions about on-chip termination in Altera® Stratix™ devices are listed below.
Which types of on-chip termination are supported by Stratix and Stratix GX devices?
Three types of on-chip termination are supported:
- Series on-chip termination
- Differential on-chip termination
- High-speed serial interface (HSSI) differential on-chip termination (Stratix GX only)
Parallel on-chip termination is not supported.
Can I use external termination resistors if I want to?
Yes. You can use external termination resistors with Stratix devices; you do not have to use on-chip termination.
Can I use external termination resistors and on-chip termination in the same I/O bank?
Yes. Because on-chip termination can be selected on a pin-by-pin basis, you can use them with external termination resistors in the same I/O bank.
Which differential I/O standards are supported with differential on-chip termination?
Differential on-chip termination supports only 137-ohms or the LVDS I/O standard. In addition, HSSI differential on-chip termination supports 100-ohms, 120-ohms, and 150-ohms terminations for the LVDS, pseudo current mode logic (PCML), and LVPECL I/O standards.
Do I need external reference resistors for series on-chip termination?
No. Series on-chip termination is implemented through programmable drive strength, and does not require external reference resistors.
Do I need external reference resistors for LVDS termination?
No. External reference resistors are not required for LVDS termination.
Which I/O banks support differential on-chip termination?
Only the left and right banks support differential on-chip termination. Additionally, HSSI differential on-chip termination is only supported in the Stratix GX transceiver blocks.
What impact does the use of on-chip termination have on the device's power consumption?
The use of series and differential on-chip termination will have minimum impact on a device’s power consumption. However, use of parallel on-chip termination will dramatically increase the power consumption of the device. A typical application with 80-bit busses using SSTL 2 Class II will dissipate over 2 watts of additional power.
Where can I find more information about on-chip termination?
See the Using High-Speed Differential I/O Interfaces chapter of the Stratix Device Handbook for detailed information about on-chip termination in Stratix devices.
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