The specification for on-chip termination in Stratix™ and Stratix GX devices has been updated. Table 1 summarizes the changes to the on-chip termination support.
| Table 1. On-Chip Termination Support Update (1) | |||
| Termination Schemes | Devices | Initial Specified Support | Current Status |
|---|---|---|---|
| Series | Stratix Stratix GX |
Yes | Updated Specification |
| Parallel | Stratix Stratix GX |
Yes | Not Available |
| Differential | Stratix Stratix GX |
Yes | Updated Specification |
| High-Speed Differential | Stratix GX | Yes | Available |
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For more information about Stratix devices, see the Stratix FPGA Family Errata Sheet and the Stratix Device Handbook.
For more information about Stratix GX devices, see the Stratix GX literature page, and contact Altera for the Stratix GX Errata Sheet to be sent to you.
Are You Using On-Chip Termination?
If you are using on-chip termination in a current design, Altera would like to assist you. Please provide contact information and your Altera support representative will call you. Or, if you would prefer, contact your Altera technical support representative.
Series On-Chip Termination
Series on-chip termination specifications have been updated to reflect silicon performance using programmable drive strength. The HSPICE models correlate well to silicon and the I/O buffers have been tested extensively with multiple channels, jitter, and logic element (LE) noise over process, voltage, and temperature (PVT) using on-chip termination. Altera recommends that users implement the series on-chip termination feature with appropriate simulations. For stringent tolerance requirements, Altera recommends using external resistors to implement series termination.
Parallel On-Chip Termination
Parallel on-chip termination does not conform to the +/- 10% specification, and the HSPICE models do not correlate to silicon. Altera recommends that external resistors be used to implement parallel termination.
Differential On-Chip Termination
Differential on-chip termination specifications have been updated to reflect silicon performance. The HSPICE models correlate well to silicon and the I/O buffers have been extensively tested with multiple channels, jitter, and LE noise over process, PVT using on-chip termination. Altera recommends that users implement the differential on-chip termination feature with appropriate simulations.
High-Speed Differential On-Chip Termination (Stratix GX Devices Only)
High-speed differential on-chip termination conforms to specifications and the HSPICE models correlate well to silicon. The I/O buffers have been extensively tested with multiple channels, jitter, and LE noise over PVT using on-chip termination. Altera recommends that users implement the high-speed serial interface (HSSI) differential on-chip termination feature with appropriate simulations.
Quartus II Software Support
The parallel on-chip termination feature will be removed in the next release of the Quartus II software.
Document Updates
The following documents have been updated with the latest information on Stratix and Stratix GX on-chip termination.
- Updated Stratix FPGA Family Errata Sheet
- Updated Literature: Stratix Device Handbook
- On-Chip Termination Questions & Answers
- AN 336: Using External Series and Parallel Termination with Stratix and Stratix GX Devices, which includes:
- Board Schematics
- Board Layout Example
- Recommendations for Small Form Factor External Resistors
Related Links
- Provide contact information for Altera support
- Contact your Altera technical support representative
