Stratix Clock Management Features
Stratix™ devices are the first FPGAs to offer on-chip phase-locked loop (PLL) features previously found only in high-end discrete PLL devices--features such as spread-spectrum clocking, clock switchover, frequency-synthesis, programmable phase shift, programmable delay shift, external feedback, and programmable bandwidth. Stratix PLLs increase system and device performance and provide advanced clock interfacing and clock-frequency synthesis. In addition, Stratix devices offer PLL reconfiguration that allows the user to change the PLL configuration without reprogramming the entire device.
Spread-Spectrum Clocking
To reduce electromagnetic interference (EMI) in a system, the enhanced PLLs in Stratix devices implement spread-spectrum technology. This technology works by distributing the clock energy over a broad frequency range. Spread-spectrum clocking schemes spread the fundamental clock frequency energy to minimize energy peaks at specific frequencies. By reducing the spectrum peak amplitudes, the system will more likely meet EMI emission compliance standards and reduce costs associated with traditional EMI containment. The enhanced PLL typically provides 0.5% down-spread modulation.
Clock Switchover
Considering the reliability requirements for today's networking systems, designers are pushed to create highly reliable systems to avoid the high costs of down time. Implementing redundant clocking schemes is one effective method used to create a highly reliable system. The Stratix PLLs support a flexible clock switchover capability that allows a redundant clock to drive the PLL should the original clock fail. Clock switchover feature can also be used for switching between clock inputs of different frequencies. Clock switchover is useful for video applications that require a manual switch between operation frequencies. The clock switchover capability is widely implemented in telecom, storage and server markets, as these markets require highly reliable clocking schemes to insure system reliability.
Figure 1 is a block diagram of the Stratix clock switchover circuitry.
Figure 1. Stratix Clock Switchover Circuitry
PLL Reconfiguration
PLL reconfiguration gives designers flexibility in multiplying or dividing input clock frequencies to achieve higher or lower output clock frequencies and allows real-time variations of the PLL frequency and output clock skew. Stratix frequency synthesis and programmable delay features can be changed by users on-the-fly; for example, designers can modify the PLL output frequencies and clock delays in prototype environments. This feature allows for PLL reconfiguration without reprogramming the rest of the chip. Furthermore, during system debugging, users can change the PLL parameters to optimize the system timing.
Frequency Synthesis
Stratix device's PLLs offer frequency synthesis a capability where input clock can be multiplied and divided to achieve a new internal clock frequency. Each Stratix PLL supports up to 10 unique output clock frequencies allowing the designers to manage multiple on and off-chip clock domains. Frequency synthesis is an essential feature enabling the support of high-speed interface standards, such as the HyperTransport™ and RapidIO standards, which use half-rate clocking schemes.
Programmable Phase & Delay Shift
The programmable phase shift feature allows designers to adjust the input clock phase by steps down to 160 ps. This feature enables designers to manage strict timing margins so that designers can meet high-speed interface requirements. The fine-tune programmable delay shift feature provides advanced timing delay shift control on each of the PLL outputs. Using discrete delay elements, each PLL output shifts in 250-ps increments for a range of -3.0 ns to +3.0 ns between any two outputs. Programmable delay shift allows designers to meet strict I/O timing requirements by giving them the option to adjust the clock to optimize tCO or tSU.
External Feedback
Stratix PLLs can drive off-chip. The external feedback feature allows designers to adjust the off-chip clock automatically to compensate for board skew. External feedback ensures system stability by allowing the PLL to adjust the external clock output during operation to account for delay changes from temperature or voltage fluctuations. Using external feedback, designers can compensate for board delay to ensure that clock edges arrive at every external clock destination simultaneously.
Programmable Bandwidth
The PLL's bandwidth is a measure of its ability to track the input clock and jitter. When using Stratix devices, designers can let the Quartus® II software set the minimum and maximum bandwidth automatically, or they can manually control the bandwidth settings within the software to filter out the desired amount of jitter from the input clock. A high-bandwidth PLL can quickly lock onto a reference clock and react to any changes in the clock. A low-bandwidth PLL will take longer to lock, but will filter more jitter. This feature offers great flexibility when the application requires cascading PLLs.
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