Signal integrity has become crucial in digital design because system speeds and clock edge rates continue to increase. To improve signal integrity, both single-ended and differential signals should be properly terminated. Termination can be implemented with external termination resistors on a board or with on-chip termination technology. Figure 1 compares the integrity of a signal without termination against a signal using Stratix™ on-chip termination.
Figure 1. Stratix On-Chip Termination Improves Signal Integrity
Altera’s Stratix devices support both on-chip termination and external termination schemes, as shown in Table 1.
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Table 1: Termination Solutions Support | ||
|
Termination Type |
On-Chip |
External |
|
Series |
Yes |
Yes |
|
Parallel |
No |
Yes |
|
Differential |
Yes |
Yes |
On-Chip Termination and Off-Chip Termination Benefits
On-chip termination eliminates the need for external resistors and simplifies the design of a printed circuit board (PCB); Stratix on-chip termination benefits are described in Table 2.
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Table 2: Benefits of Stratix On-Chip Termination | |
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Benefit |
Description |
|
Improved Signal Integrity |
On-chip termination eliminates stub effects and helps to prevent reflections on the transmission line. |
|
Simpler Board Design |
On-chip termination minimizes the need for external resistors , allowing designers to use fewer resistors, fewer board traces, and less board space, resulting in a simpler board layout. |
|
Lower Cost |
With on-chip termination, fewer resistors, fewer traces, and less space are needed on the board. System designers spend less time in layout. Reducing the designer's layout time and the number of components on the board can result in lower overall system costs. |
|
Increased System Reliability |
System reliability increases because on-chip termination reduces the number of components on the PCB. |
Termination with external resistors, on the other hand, provides tighter tolerance and is recommended for designs with stringent impedance tolerance requirements. Altera provides an external termination design kit with recommendations for low-cost, small form factor resistor packs, board schematics and layout examples, along with simulation and test results. Figure 2 shows how off-chip termination is implemented using resistor packs.
Figure 2. Off-Chip Termination Using Resistor Packs
Series Termination
Stratix devices support on-chip series termination for LVTTL, LVCMOS, SSTL-18 and SSTL-2 single-ended I/O standards (shown in Table 3). The on-chip termination is provided at the output signal to match the impedance of the transmission line, typically 25Ω or 50Ω. Designers can use this termination in many general-purpose applications and to interface with double data rate (DDR) SDRAM memories.
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Table 3: Supported I/O Standards for Series Termination | |
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Standard |
Resistance ( |
|
3.3-V, 2.5-V, 1.8-V, 1.5-V LVTTL |
25 or 50 |
|
3.3-V, 2.5-V, 1.8-V, 1.5-V LVCMOS |
25 or 50 |
|
SSTL-18, SSTL-2 (Class I) |
25 |
|
SSTL-18, SSTL-2 (Class II) |
25 |
)Parallel Termination
Stratix devices support parallel termination through external resistors. Altera provides an external termination design kit with recommendations for low-cost, small-form factor resistor packs, board schematics and layout examples, along with simulation and test results.
Differential Termination
Designers use differential termination in system applications that require support for high-speed interface protocols, such as SPI-4.2, SFI-4, XSBI, RapidIO™, HyperTransport, NPSI, and UTOPIA IV standards.
Stratix devices support LVDS and HyperTransport™ input on-chip differential termination. The value of the on-chip termination resistor shown in Figure 3, RD, is 100 
.
Figure 3. On-Chip Differential Termination
Related Links
- AN 336: Using External Series and Parallel Termination with Stratix and Stratix GX Devices
- Using Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook
- AN 224: High-Speed Board Layout Guidelines
- Differential On-Chip Termination Questions & Answers
- Board Design Solution Center
- Parallel I/O Technology Center
