Stratix Architectural Efficiency

Design efficiency can be defined as the effectiveness of an FPGA in fitting a design using minimum logic resources. Design efficiency depends upon the FPGA architecture, device resources, and development tools used for synthesis and place-and-route.

Altera^® Stratix^™ FPGAs were designed from the ground up to provide the optimum logic, memory, and routing architecture needed for complex system-on-a-programmable-chip (SOPC) designs. Stratix FPGAs, combined with Altera development tools, provide more efficient design implementation than competing FPGA devices, allowing designers to utilize smaller and lower-cost devices with ample resources.

Comparing Logic Resources

The basic programmable logic function in Altera's Stratix devices and Xilinx's Virtex-II Pro devices contains a register and a 4-input look-up table (LUT). Each architecture also has unique logic functions such as adders, carry chains, and multiplexers tied to the LUT to increase logic efficiency. While the associated logic is different between the competitive products, the LUT is the only common unit for comparing design efficiency between FPGA families.

Recently, Xilinx published a white paper comparing the efficiency of the Virtex-II Pro and Stratix device architectures by doing a low-level architectural analysis of both devices. This approach is similar to a comparison that was done between CISC and RISC microprocessors 20 years ago that originally concluded that RISC architectures had higher performance than CISC architectures because they had faster clock rates. However, real applications benchmarks showed that CISC architectures were, in fact, the more powerful architecture. Therefore, low-level architectural analysis proves to be a flawed method of analysis. The best method of comparison is to benchmark performance using real applications.

Architectural Efficiency Benchmarks

To compare the architectural efficiency of the Stratix FPGA and the Virtex-II Pro FPGA, Altera implemented 97 customer designs into both products. The percentage of logic resources used in each device was determined from the respective report files and compared. The results are shown in Figure 1.

Figure 1. Design Benchmark Results

On average, Virtex-II Pro FPGAs require 9% more LEs than Stratix FPGAs based on LUT count. While the benchmarks show typical results, individual results will vary with each design. For more information on this benchmark analysis, refer to the An Analytical Review of FPGA Logic Efficiency in Stratix, Virtex-II & Virtex-II Pro Devices White Paper, which compares the resource utilization efficiency of Stratix FPGAs with Virtex-II and Virtex-II Pro FPGAs.

Measuring Virtex-II Pro: LUTs vs. Logic Cells

Altera and Xilinx use two different metrics to measure the capacity of their FPGAs. Xilinx uses a metric called the logic cell (LC), while Altera uses the logic element (LE). LCs and LEs are not equal metrics and cannot be compared as such. In fact, the number of LCs is 12.5% more than the number of LUTs (while the number of LEs are equal to the number of 4-input LUTs). The effect of using LCs is to make the Virtex-II Pro devices appear 12.5% larger than they actually are.

Table 1 shows the LUT and LC count for all of the Virtex-II Pro devices as well as the LUT and LE count for Stratix devices.

Conclusion

Using LCs to measure and compare the capacity of Virtex-II Pro devices serves no purpose. LCs are merely units of measurement that make the Virtex-II Pro devices look 12.5% larger than they actually are. Additionally, Altera's benchmark results show that on average, Stratix devices consume 9% fewer LUTs than Virtex-II Pro devices.

Figure 2 shows a comparison of actual logic capacity in Stratix and Virtex-II Pro devices.

Figure 2. Logic Capacity for Stratix & Virtex-II Pro Devices

Notes:

1. Effective number of LUTs normalized to Altera LE.
2. Normalized to number of LUTs.

Related Links

• An Analytical Review of FPGA Logic Efficiency in Stratix, Virtex-II & Virtex-II Pro Devices