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Home > Products > Devices > Stratix (and GX) > Stratix > Overview Print This Page Subscribe to Email Stratix Device Family Overview The original generation of Stratix® devices, for most applications, is superseded by later Stratix device family generations. Designers needing higher performance, higher density, and lower cost will benefit from using the award winning, 90-nm Stratix II devices. The newest generation Stratix III devices are based on a 65-nm process and are designed to provide the performance and features needed for future high-end, high-bandwidth systems. For military applications, the original generation of Stratix devices is still the high-density solution of choice. The Stratix device family is optimized to address the challenges of high-bandwidth systems. Stratix devices offer high core performance, memory capacity, architectural efficiencies, and time-to-market advantages. Stratix devices offer dedicated functionality for clock management and digital signal processing (DSP) applications, as well as support for differential and single-ended I/O standards. In addition, Stratix devices offer on-chip termination and remote system upgrade capabilities. The Stratix device family is a feature-rich, high-bandwidth system solution that takes system-on-a-programmable-chip (SOPC) solutions to the next level. Based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, Stratix devices are available in densities ranging from 10,570 to 79,040 logic elements (LEs) and up to 7 Mbits of RAM. Stratix devices offer up to 22 DSP blocks with up to 176 (9-bit x 9-bit) embedded multipliers, optimized for complex applications that require high data throughput. Stratix devices also offer the True-LVDS circuitry to support the LVDS, LVPECL, PCML, and HyperTransport™ differential I/O electrical standards, as well as high-speed communication interfaces, including the 10G Ethernet XSBI, SFI-4, POS-PHY Level 4 (SPI-4 Phase 2), HyperTransport, RapidIO®, and UTOPIA IV standards. The Stratix FPGA family offers a complete clock management solution with its hierarchical clock structure and up to 12 phase-locked loops (PLLs). System designers requiring a low-risk cost-reduction path for high-volume production can easily migrate their Stratix FPGA designs to mask-programmed HardCopy® Stratix devices. HardCopy Stratix devices significantly minimize migration risk because they are generated directly from the Stratix FPGA and preserve the Stratix architecture's high density, high performance, industry-leading functionality, and enhanced timing features. This seamless migration process guarantees first-time success for high-volume production, allowing system designers to improve time-to-market at the lowest cost. Stratix II FPGAs are supported by HardCopy II ASICs in a similar seamless migration path to high-volume, low-cost, high-density logic requirements. Table 1 outlines the Stratix device family members and features. Table 2 shows an overview of Stratix device packaging and I/O pin counts. Table 3 shows the appropriate configuration devices to use for each Stratix device family member. Table 1. Stratix Device Overview Feature Device EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 Logic Elements (LEs) 10,570 18,460 25,660 32,470 41,250 57,120 79,040 M512 RAM Blocks (512 Bits + Parity) 94 194 224 295 384 574 767 M4K RAM Blocks (4 Kbits + Parity) 60 82 138 171 183 292 364 M-RAM Blocks (512 Kbits + Parity) 1 2 2 4 4 6 9 Total RAM bits 920,448 1,669,248 1,944,576 3,317,184 3,423,744 5,215,104 7,427,520 DSP Blocks 6 10 10 12 14 18 22 Embedded Multipliers (1) 48 80 80 96 112 144 176 PLLs 6 6 6 10 12 12 12 Maximum User I/O Pins 426 586 706 726 822 1,022 1,203 Production Device Availability Buy Now Buy Now Buy Now Buy Now Buy Now Buy Now Buy Now Note: Total number of 9 x 9 multipliers. To obtain the total number of 18 x 18 multipliers per device, divide the total number of 9 x 9 multipliers by a factor of 2. To obtain the total number of 36 x 36 multipliers per device, divide the total number of 9 x 9 multipliers by a factor of 8. Table 2. Stratix Device Package and Maximum User I/Os Package Size (mm x mm) Device EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 672-Pin BGA 35 x 35 345 426 473 - - - - 956-Pin BGA 40 x 40 - - - 683 683 683 683 484-Pin FineLine BGA 23 x 23 335 361 - - - - - 672-Pin FineLine BGA 27 x 27 345 426 473 - - - - 780-Pin FineLine BGA 29 x 29 426 586 597 597 615 - - 1,020-Pin FineLine BGA 33 x 33 - - 706 726 773 773 773 1,508-Pin FineLine BGA 40 x 40 - - - - 822 1,022 1,203 Table 3. Appropriate Configuration Devices for Stratix Devices Configuration Device Number of Devices EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 EPC2 3 4 5 7 8 11 15 EPC4 1 1 - - - - - EPC8 1 1 1 1 1 - - EPC16 1 1 1 1 1 1 1 Contact Altera Altera sells programmable logic devices (PLDs) exclusively through sales representatives and distributors. Please contact your Altera® sales representative or distributor listed below. Altera Sales Offices North American Sales Offices International Sales Offices Distributors and Representatives North American Distributors U.S. Sales Representatives International Distributors Related Links Stratix Device Handbook HardCopy Stratix ASICs HardCopy II ASICs Performance in High-Density FPGAs Benchmarking Methodology Rate This Page

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