Stratix Device Family Overview

The original generation of Stratix^® devices, for most applications, is superseded by later Stratix device family generations. Designers needing higher performance, higher density, and lower cost will benefit from using the award winning, 90-nm Stratix II devices. The newest generation Stratix III devices are based on a 65-nm process and are designed to provide the performance and features needed for future high-end, high-bandwidth systems. For military applications, the original generation of Stratix devices is still the high-density solution of choice.

The Stratix device family is optimized to address the challenges of high-bandwidth systems. Stratix devices offer high core performance, memory capacity, architectural efficiencies, and time-to-market advantages. Stratix devices offer dedicated functionality for clock management and digital signal processing (DSP) applications, as well as support for differential and single-ended I/O standards. In addition, Stratix devices offer on-chip termination and remote system upgrade capabilities. The Stratix device family is a feature-rich, high-bandwidth system solution that takes system-on-a-programmable-chip (SOPC) solutions to the next level. Stratix devices also offer industrial temperature support.

Based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, Stratix devices are available in densities ranging from 10,570 to 79,040 logic elements (LEs) and up to 7 Mbits of RAM. Stratix devices offer up to 22 DSP blocks with up to 176 (9-bit x 9-bit) embedded multipliers, optimized for complex applications that require high data throughput. Stratix devices also offer the True-LVDS circuitry to support the LVDS, LVPECL, PCML, and HyperTransport™ differential I/O electrical standards, as well as high-speed communication interfaces, including the 10G Ethernet XSBI, SFI-4, POS-PHY Level 4 (SPI-4 Phase 2), HyperTransport, RapidIO^®, and UTOPIA IV standards. The Stratix FPGA family offers a complete clock management solution with its hierarchical clock structure and up to 12 phase-locked loops (PLLs).

System designers requiring a low-risk cost-reduction path for high-volume production can easily migrate their Stratix FPGA designs to mask-programmed HardCopy^® Stratix devices. HardCopy Stratix devices significantly minimize migration risk because they are generated directly from the Stratix FPGA and preserve the Stratix architecture's high density, high performance, industry-leading functionality, and enhanced timing features. This seamless migration process guarantees first-time success for high-volume production, allowing system designers to improve time-to-market at the lowest cost. Stratix II FPGAs are supported by HardCopy II ASICs in a similar seamless migration path to high-volume, low-cost, high-density logic requirements.

Table 1 outlines the Stratix device family members and features. Table 2 shows an overview of Stratix device packaging and I/O pin counts. Table 3 shows the appropriate configuration devices to use for each Stratix device family member.

Note:

1. Total number of 9 x 9 multipliers. To obtain the total number of 18 x 18 multipliers per device, divide the total number of 9 x 9 multipliers by a factor of 2. To obtain the total number of 36 x 36 multipliers per device, divide the total number of 9 x 9 multipliers by a factor of 8.

Table 4 shows industrial temperature support for Stratix FPGAs.

Contact Altera

Altera sells programmable logic devices (PLDs) exclusively through sales representatives and distributors. Please contact your Altera^® sales representative or distributor listed below.

Altera Sales Offices

• North American Sales Offices
• International Sales Offices

Distributors and Representatives

• North American Distributors
• U.S. Sales Representatives
• International Distributors

Related Links

• Stratix Device Handbook
• HardCopy Stratix ASICs
• HardCopy II ASICs
• Performance in High-Density FPGAs
• Benchmarking Methodology