Automatic Cyclic Redundancy Code Checking in Stratix FPGAs
Stratix® devices are the first FPGAs to offer on-chip circuitry for automated checking of Cyclic Redundancy Code (CRC). Some critical applications require periodic CRC checks to ensure continued data integrity in a high reliability environment.
Checking CRC ensures data reliability and is one of the best techniques in mitigating single event upset (SEU) problems. This Stratix feature can be easily implemented for all designs at no extra cost and eliminates the need for complex external logic. A Quartus® II-computed CRC is loaded into the device during configuration, and dedicated circuitry checks it against an automatically computed CRC. The CRC_error pin reports failure when configuration RAM data is changed unintentionally and makes it easy to trigger re-configuration.
Custom-Built Circuitry
Dedicated circuitry in Stratix devices continually and automatically checks for CRC errors in the configuration SRAM cells while the device is in user mode. Designers can monitor one external pin for the error and use it for re-configuration. Clock frequency can be changed by modulating the clock divider to select the desired checking period.
Simple Software Interface
Just one simple click turns on automatic CRC checking in Quartus II version 4.1 software.
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