Digital Signal Processing (DSP) Blocks in Stratix Devices
FPGAs are becoming a powerful tool for implementing high-performance digital signal processing (DSP) applications. With the ability to support large number of parallel multipliers, FPGAs provide the best performance compared to alternative implementations. The DSP blocks in Stratix™ devices are high-performance embedded DSP units optimized for applications such as:
- Rake receivers
- Voice over Internet protocol (VoIP) gateways
- Orthogonal frequency division multiplexing (OFDM) transceivers
- Image processing applications
- Multimedia entertainment systems (as shown in Figure 1)
The DSP blocks eliminate performance bottlenecks in DSP applications, provide predictable and reliable performance, and result in resource savings without compromising performance. Altera® Stratix devices use DSP blocks to achieve the high data throughput necessary for computationally demanding applications. In fact, the DSP blocks in Stratix devices run at 333 MHz to provide data throughput performance of 2.67 giga multiply-accumulate operations per second per DSP block with minimal routing congestion. Additionally, the 22 DSP blocks of the largest Stratix device, the EP1S80 device, can provide a combined throughput of up to 58.6 giga multiply-accumulate operations per second—more than 10 times the data throughput available from leading digital signal processors today.
Figure 1. Stratix DSP Blocks for Multiple Applications
DSP Block Architecture
Stratix DSP blocks consist of hardware multipliers, adders, subtractors, accumulators, and pipeline registers. Stratix DSP blocks provide optimal performance due to their dedicated circuitry, as shown in Figure 2. The dedicated circuitry incorporates optimized embedded multipliers that maximize performance of the DSP blocks.
Figure 2. DSP Block
Each DSP block is optimized for maximum performance of up to 333 million samples per second (MSPS) per block allowing for efficient implementation of high-precision DSP functions. For example, a 180-tap, 5 MSPS finite impulse response (FIR) filter shown in Figure 3 can be implemented within a single DSP block using external add-accumulate circuitry as shown in Figure 4. Further, these DSP blocks have been optimized to interface with the specialized memory structures in Stratix devices for memory-intensive DSP applications.
Figure 3. 180-Tap FIR Filter Circuit
Figure 4. Single DSP Block-Based Implementation
Multipliers
Each DSP block in a Stratix device can implement four 18x18-bit multiplications using dedicated multiplier circuitry. Each DSP block can also be configured to support eight 9x9-bit multiplication or one 36x36-bit multiplication for different applications by choosing the appropriate DSP block operation mode in the Quartus® II software. While configured in the 36x36 mode, the DSP block can also perform floating-point arithmetic.
The dedicated multiplier circuitry supports signed and unsigned multiplication operations, and can dynamically switch between the two without any loss of precision.
Adder/Subtractor/Accumulator Unit
The adder/subtractor/accumulator unit can be configured as an adder, a subtractor, or as an accumulator, based on its operation mode. This unit can automatically switch between adder and subtractor functionality, acting as a 9-bit, 18-bit, or a 36-bit adder as necessary. In the accumulator mode, the unit acts as a 52-bit accumulator.
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