TriMatrix Memory in Stratix Devices
 Stratix™ devices feature the TriMatrix™ memory structure, composed of three sizes of embedded RAM blocks. TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit M-RAM blocks, each of which can be configured to support a wide range of features. Offering up to 7 Mbits of RAM and up to 8 terabits per second of device memory bandwidth, the TriMatrix memory structure makes the Stratix device family an ideal choice for memory-intensive applications.
The TriMatrix memory offers different memory structures that can implement a wide variety of memory functions found in complex designs. Designers can use the smaller M512 RAM blocks for first-in first-out (FIFO) functions and clock domain buffering where memory bandwidth is critical. The revolutionary M-RAM block addresses the FPGA requirement for large buffering applications such as intellectual property (IP) packet buffering and system cache. The M4K blocks are ideal for medium-sized memory applications such as asynchronous transfer mode (ATM) cell processing. Figures 1 and 2 show the TriMatrix memory structure and a variety of its applications.
Figure 1. TriMatrix Memory Structure
Figure 2. TriMatrix Memory Applications
High Memory Bandwidth & Density
Stratix devices offer the highest memory-to-logic ratio of any FPGA family, made possible by the area-efficient M-RAM blocks. Just as importantly, Stratix devices offer the smaller M512 and M4K blocks that offer 18-bit- and 36-bit-wide data ports per block respectively, offering the highest FPGA memory bandwidth and making them ideal for applications requiring extensive accessibility to the memory resources.
Memory bandwidth measures the amount of data that can pass through a memory block and is defined as the product of the M-RAM blocks' memory data port width and performance. With over 28,000 data ports in the EP1S80 device, each one capable of transferring data rates over 285 MHz, Stratix devices provide unmatched memory bandwidth at 8 terabits per second (as shown in Table 1).
| Table 1: Stratix Device Bandwidth (1) |
| Device |
Logic Elements |
Total RAM Bits |
M-RAM Blocks
(512-Kbits) |
M4K Blocks
(4-Kbits) |
M512 Blocks
(512-bits) |
Total Memory Bandwidth
(Mbps) |
| EP1S10 |
10,570 |
920,448 |
1 |
60 |
94 |
1,245,024 |
| EP1S20 |
18,460 |
1,669,248 |
2 |
82 |
194 |
2,096,928 |
| EP1S25 |
25,660 |
1,944,576 |
2 |
138 |
224 |
2,894,400 |
| EP1S30 |
32,470 |
3,317,184 |
4 |
172 |
295 |
3,750,192 |
| EP1S40 |
41,250 |
3,423,744 |
4 |
183 |
384 |
4,384,800 |
| EP1S60 |
57,120 |
5,215,104 |
6 |
292 |
574 |
6,762,528 |
| EP1S80 |
79,040 |
7,427,520 |
9 |
364 |
767 |
8,784,720 |
Note:
- Does not include additional bandwidth figures associated with external memory device interfaces.
The RAM blocks in the high-performance TriMatrix memory structure offer the following features:
- True dual port for complex memory functions
- Parity-bits
- Embedded shift register functionality
- Mixed-clock mode
- Byte-enabled support
- Mixed-width support
- Configurable memory width dimensions for each of the RAM blocks (as shown in Table 2)
| Table 2: TriMatrix Memory Features |
| Memory Feature |
M512 Blocks
512-bits + parity |
M4K Blocks
4-Kbits + parity |
M-RAM Blocks
512-Kbits + parity |
| Maximum Performance |
319 MHz |
290 MHz |
287 MHz |
| True Dual Port Memory |
|
 |
|
| Simple Dual-Port memory |
|
|
|
| Single-Port Memory |
|
|
|
| Byte Enable |
|
|
|
| Parity Bits |
|
|
|
| Shift Register |
|
|
|
| Mixed-Clock Mode |
|
|
|
| Configurations |
512 x 1
256 x 2
128 x 4
64 x 8
64 x 9
32 x 16
32 x 18 |
4K x 1
2K x 2
1K x 4
512 x 8
512 x 9
256 x 16
256 x 18
128 x 32
128 x 36 |
64K x 8
64K x 9
32K x 16
32K x 18
16K x 32
16K x 36
8K x 64
8K x 72
4K x 128
4K x 144 |
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