Source Synchronous Signaling I/O Standards in Stratix II Devices
Stratix® II devices offer up to 152 receiver and 156 transmitter channels that support source-synchronous signaling for data transfer rates as high as 1.040 Gbps. Stratix II devices support the requirements of high-speed I/O protocols such as SPI-4.2, HyperTransport™ technology, the RapidIO™ standard, Network Processing Forum (NPF) Streaming Interface (NPSI), SFI-4, and 10-gigabit 16-bit interface (XSBI) Ethernet. Designers can use Stratix II devices to create high-performance bridging functions between devices that use these I/O protocols.
As high-speed interfaces with source-synchronous clocking schemes approach 1 Gbps transfer rates, the margin for clock-to-channel and channel-to-channel skew contracts significantly. To stay within the permitted skew, designers must use precise printed circuit board (PCB) design techniques because any mismatch in trace lengths could result in erroneous data transfer. Other effects—such as jitter, temperature, and voltage variations—compound the problem, making simpler, static phase alignment techniques ineffective. Altera recognizes the challenges that engineers face when designing systems that transfer high-speed data and has incorporated dynamic phase alignment (DPA) circuitry in Stratix II devices to dramatically simplify PCB design, eliminating the signal alignment problems introduced by skew-inducing effects.
Stratix II DPA
The DPA circuitry eliminates clock-to-channel skew by aligning a sampling clock with the incoming data, as shown in Figure 1.
Figure 1. Stratix II Source-Synchronous Channels Support 1 Gbps
Notes:
- PLL = phase-locked loop
- FIFO = first in, first out
- SERDES = serializer/deserializer
Using one of eight phase-shifted clocks generated by the fast PLL, the dynamic phase aligner samples the incoming data and aligns the data by choosing the clock phase that is closest to the center of the incoming data. This alignment is continuous and can compensate for dynamic changes in the real-time timing variations between the clock and data signals.
The DPA circuitry supports multiple SERDES factors including the 3x to 10x modes. Each channel has its own DPA circuit that provides independent data alignment for each channel; therefore, DPA can eliminate channel-to-channel skew as well as clock-to-channel skew, as shown in Figure 2.
Figure 2. Skew Correction With DPA Circuitry
Table 1 summarizes the DPA timing specifications in Stratix II devices.
|
Table 1. DPA Specifications in Stratix II Devices
|
| Parameter |
Value |
| Data Rate |
|
| Clock Frequency Range |
|
| High-Speed Protocols Supported |
- SPI-4.2
- RapidIO
- NPSI
- SFI-4
- HyperTransport
- 10 Gigabit Ethernet XSBI
|
| Signaling Levels |
|
Differential I/O Standards
The Stratix II source-synchronous circuitry supports the LVDS and HyperTransport differential I/O standards. Designers often use these standards for high-performance applications to create better noise margins, provide lower electromagnetic interference (EMI), and lower power consumption. Additionally, these standards support the high data throughput needed for high-speed interface standards, such as HyperTransport technology, the RapidIO standard, NPSI, SPI-4.2, SFI-4, 10 Gigabit Ethernet XSBI, and UTOPIA Level 4. Table 2 summarizes the differential I/O standards, maximum performance rates, and applications supported by Stratix II devices.
| Table 2. Differential I/O Standards Support in Stratix II |
| I/O Standard |
Performance (Gbps) |
Typical Application |
| LVDS |
1.040 |
Backplane |
| HyperTransport |
1.040 |
Host Processor |
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