ASIC Prototyping with Stratix III FPGAs
Designing leading-edge ASICs in today's world is becoming an ever more expensive and time-consuming operation due to the increasing cost of mask-sets and the amount of engineering verification required. Getting a device right the first time is imperative. A single missed deadline can mean the difference between profitability and failure in the life cycle of a product. Figure 1 shows how the sales of a product can be affected due to time-to-market delays.
Figure 1. Declining Product Sales Due to Late-to-Market Designs
Using FPGAs to prototype an ASIC or ASSP for verification of both register transfer level (RTL) and initial software development is now becoming standard practice to both decrease development time and reduce the risk of first silicon failure. An FPGA prototype accelerates verification by allowing testing of a design on silicon from day one, months in advance of final silicon becoming available. Code can be compiled for the FPGA, downloaded, and debugged in hardware during both the design and verification phases using a variety of techniques and readily available solutions. Whether you're doing RTL validation, initial software development, and/or system level testing, FPGA prototyping platforms deliver a higher degree of confidence in your ability to deliver an end working product. For more on this topic, explore the related links listed below.
Altera® Stratix® III FPGAs are ideal for ASIC prototyping, offering the highest density of any FPGA available today. Designs of up to 4+ million ASIC gates (i.e. 2-input NAND gates) plus 16 Mbits of memory and 576 digital signal processing (DSP) blocks available as additional resources can be implemented in a single Stratix III EP3SL340 device. Details of the larger Stratix III FPGAs are shown in Table 1.
| Table 1. Largest Devices of Stratix III FPGA Family |
| Device |
Logic Elements (LEs) |
ASIC Gates |
User I/Os |
Total
Memory
Bits |
18 x 18
Multipliers |
Phase-Locked Loops (PLLs) |
| EP3SL150 |
142,000 |
1.7M |
744 |
5.5M |
384 |
8 |
| EP3SL200 |
198,900 |
2.4M |
976 |
7.7M |
576 |
12 |
| EP3SE260 |
254,400 |
3.1M |
976 |
14.6M |
768 |
12 |
| EP3SL340 |
338,000 |
4.1M |
1104 |
16.3M |
576 |
12 |
For the larger ASIC designs that don't fit into a single FPGA, using multiple FPGAs for prototyping becomes a matter of partitioning a design across FPGAs and ensuring design interconnects (e.g., bus signals) are maintained. Using the biggest FPGA available reduces the number of FPGAs required to implement a prototype, which means a reduction in the number of interconnects required between devices. Fewer low-speed paths are added to the design because of PCB traces, and hence the performance of the FPGA prototype is as close to the design goals for the final ASIC as possible.
To aid and support the development of high-density designs, Altera has developed an ecosystem of EDA software partners and development board partners that help facilitate the complete design process.
Stratix III devices are fully supported by major ASIC EDA vendors for software solutions as well as third-party board vendors for off-the-shelf multi-FPGA solutions. Altera's Quartus® II design software integrates into design flows that are close to, if not identical to, a typical ASIC flow, reducing the amount of learning required when using a new software tool. In addition, the tools can be invoked using scripting to match commonly used ASIC design methodologies.
Stratix III FPGAs offer the industry's only seamless development path from FPGA prototype to high-volume, structured ASIC production with support for migration to HardCopy® ASICs. Designing for HardCopy III devices allows you to reduce development costs and still get the flexibility and time-to-market advantages associated with FPGAs.
All of the Altera intellectual property (IP) cores that support the Stratix family of devices can be licensed for use in an ASIC. The advantage of an Altera IP core is that the IP is optimized to the Stratix family architecture, allowing it to run at ASIC-like speeds.
ASIC Prototyping Third-Party Board Partners
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