Stratix II GX DSP Blocks
Stratix® II GX devices offer features such as digital signal processing (DSP) blocks, TriMatrix™ memory, and adaptive logic modules (ALMs) that are optimized for high-performance DSP applications. Stratix II GX devices are ideal for both high-speed communication over the backplane and chip-to-chip applications in many markets including communications, digital broadcast, and storage systems.
When combined with TriMatrix memory and ALMs, DSP blocks can efficiently implement DSP algorithms such as filtering, video/image processing, scaling, chip-rate processing, equalization, digital downconversion/digital upconversion (DDC/DUC), transforms, and modulation.
Stratix II GX DSP blocks are capable of running at 450 MHz and provide very high DSP throughput (up to 346 GMACs with 9-bit x 9-bit parallel multiplications). This is orders of magnitude higher than competing DSP processors available today. Using DSP blocks, Stratix II GX FPGAs can easily meet the DSP throughput requirements of emerging standards and protocols such as JPEG 2000, H.264, WM9, CDMA2000, 1x EV DV, HSDPA, W-CDMA, and WiMAX as shown in Table 1.
| Table 1. DSP Applications That Can Be Implemented Using DSP Blocks |
| Applications |
Military Applications |
Image Processing |
Communications |
| Radar/Sonar |
Broadcast & Medical |
Wireless |
| Algorithms & Functions |
- Filtering
- Transforms
- Modulation
|
- Filtering
- Compression
- Scaling
|
- Chip-Rate Processing
- Equalization
- Digital IF (DDC, DUC)
|
| Standards & Protocols |
- |
|
- HSDPA
- CDMA 2000, 1x EV DV
- WiMAX (802.16d/e)
|
DSP Block Details
The DSP block architecture has been optimized for implementing several DSP functions with maximum performance and minimum logic resource utilization. Each DSP block offers multipliers, adders, subtractors, accumulators, and a summation unit—functions that are frequently required in typical DSP algorithms. Figure 1 shows the DSP block architecture.
Figure 1. DSP Block Architecture
Each DSP block can support a variety of multiplier bit sizes (9x9, 18x18, 36x36) and operation modes (multiplication, complex multiplication, multiply-accumulation, and multiply-addition), and can offer a DSP throughput of 3.6 GMACS per DSP block. The largest Stratix II GX device, EP2SGX130, offers 63 DSP blocks that can perform up to 113.4 GMACS combined throughput with 252 18-bit x 18-bit parallel multiplications. The throughput in Stratix II GX devices is orders of magnitude higher than single-chip DSP processors available in the marketplace today.
In addition, new rounding and saturation support has been added to the DSP block to facilitate porting DSP firmware code onto the FPGA. Many applications, such as speech processing, must use rounding and saturation because of the fixed widths of the memory buffers that store the data. Previously, digital signal processor designers using fixed-point numbers and FPGAs had to modify their design to accommodate rounding and saturation. With the rounding and saturation support in DSP blocks, it is now much easier to port DSP-processor-based designs to an FPGA implementation.
The latest Quartus® II software has been further optimized for mapping signal processing algorithms onto the Stratix II GX DSP block architecture.
For more details on the DSP block feature, refer to the Stratix II GX Device Handbook or Stratix II Device Handbook.
DSP Co-Processing With Stratix II GX FPGAs
Stratix II GX FPGAs can be used to implement complete DSP systems that require high DSP throughput. They can also be used as FPGA co-processors in DSP applications for accelerating performance-critical DSP functions—these functions would otherwise consume a majority of the host processors processing power and slow down overall system performance. Stratix II GX FPGA-based co-processors can boost overall system performance by offloading complex computations such as turbo decoding, echo cancellation, multi-user detection, and correlators from the host processor.
Altera offers designers a broad range of support services, tools, and development platforms for implementing DSP designs in Stratix II GX FPGAs. User-defined FPGA co-processors can be developed quickly with DSP Builder, Altera’s data flow architecture development tool based on The MathWorks’ industry-leading MATLAB and Simulink tools. Once the co-processor architecture is captured, it can automatically be implemented into an Altera® FPGA or exported to Altera’s SOPC Builder system development tool for further integration into the overall system architecture.
Altera also offers DSP development kits that can be used to verify your DSP systems in hardware in the prototype phase of your design cycle.
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