Stratix II GX Transceiver FPGAs Overview
Stratix® II GX FPGAs with transceivers have been created to provide a robust solution for applications requiring high-speed I/O between 600 Mbps and 6.375 Gbps. Built on the success of Stratix GX FPGA transceivers, the low-power transceivers have been architected to provide excellent jitter performance and include a number of features to ensure signal integrity. Many protocols are now emerging for high-speed transceivers. With this in mind, specific features are included within the digital blocks of the device to simplify implementation of both standard and custom protocols.
Key Transceiver Features
- High-speed serial transceiver channels with clock data recovery (CDR) provides 600-Mbps to 6.375-Gbps full-duplex transceiver operation per channel
- Devices available with 4, 8, 12, 16, or 20 high-speed serial transceiver channels providing up to 255 Gbps of serial bandwidth (full duplex)
- Programmable differential output voltage (VOD) and pre-emphasis settings for improved signal integrity
- Flexible equalization with three test access ports (TAPs) allowing for 17 dB of equalization
- Support for CDR-based bus standards, including PCI Express, Gigabit Ethernet (GbE), SDI, Altera’s SerialLite II, XAUI, Serial RapidIOTM and the Optical Internetworking Forum (OIF) CEI-6G
- Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation
- Selectable on-chip termination resistors for improved signal integrity on a variety of transmission media
- Programmable transceiver-to-FPGA interface with support for 8-, 10-, 16-, 20-, 32-, and 40-bit wide data transfer
- Receiver indicator for loss of signal
- Built-in self test (BIST)
- Hot insertion/removal protection circuitry
- Rate matcher, byte-reordering, bit-reordering, pattern detector, and word aligner support programmable patterns
- Generic polarity inversion for 3G and 6G protocols and polarity inversion specifically for PCI Express
- Dedicated circuitry that is compliant with the physical interface for PCI Express (PIPE) standard, XAUI, and GbE
- Built-in byte ordering so that a frame or packet always starts in a known byte lane
- Each transmitter has two phase-locked loop (PLL) inputs and also has independent clock dividers to provide varying clock rates on each of its transmitters
- 8b/10b encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
- Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array
- Receiver FIFO buffer resynchronizes the received data with the local reference clock
Block Diagram
Figure 1 shows the block diagram of the Stratix II GX transceiver for both the physical medium attachment (PMA) and the physical coding sub-layer (PCS). The blocks within the PCS can be bypassed, depending on the user’s requirement.
Figure 1. Stratix II GX Transceiver PMA & PCS Block Diagram
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The Stratix II GX transceiver provides dedicated circuitry to implement standard protocols operating between 600 Mbps and 6.375 Gbps in native mode. The transceiver is also capable of supporting data rates as low as 270 Mbps using oversampling, which is important when supporting legacy protocols and protocols with multiple data rates. The transceiver implements key building blocks for a number of protocols including PCI Express, Gigabit Ethernet, SDI, Altera’s SerialLite II, XAUI, Serial RapidIO and OIF CEI-6G, which when augmented with Altera® intellectual property (IP) provide a complete and low risk path solution.
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