OpenCore Designs Validate—Stratix III FPGA Advantages Increase with Design Size
Benchmarks on the seven most popular and largest OpenCore designs show that, when compared to the nearest competing FPGA, Stratix® III FPGA advantages in performance, utilization and compile time increase with design size. See Table 1 for the overall benchmark results and Table 2 for the device and speed grades used for benchmarking purposes.
| Table 1. Stratix III and Quartus II Advantages Increase with Design Size |
| Feature |
Advantage Over Nearest Competing Device |
| Performance |
Increases up to 65 percent |
| Utilization |
Can fit, on average, 46 percent more logic |
| Compile Time |
3x to 9x faster
|
| Table 2. Devices and Speed Grade Benchmarked |
| FPGA |
Altera |
Xilinx |
| Device |
EP3S340-3(1)
|
XC5VLX330-2(1)
|
| Speed Grade |
Medium(2)
|
Medium(2)
|
Notes:
- Similar results are seen on smaller parts
- The medium speed grades are the fastest available in software.
At the time of the benchmarks, the seven most popular and largest designs on www.OpenCores.org were selected and are listed in Table 3 in terms of their logic element requirements. To simulate the effect of increasing design size on performance, utilization and compile times, multiple instances of each OpenCore were instantiated in the FPGAs. Care was taken in the benchmarking and stamping methodology to ensure individual cores were implemented in parallel and no timing critical paths existed between the cores and in the wrapper logic.
| Table 3. OpenCore Designs |
| OpenCores |
Logic Elements |
ALMS |
| oc_aquarius |
6475 |
2590 |
| oc_des_des3perf |
15670 |
6268 |
| oc_ethernet |
3548 |
1419 |
| oc_oc8051 |
4115 |
1646 |
| oc_or1k |
7028 |
2811 |
| oc_pci |
3630 |
1452 |
| oc_usb_funct |
4318 |
1727 |
Performance Advantage
In Figure 1, the Y-axis shows the ratio of the fMAX achieved between Stratix III FPGAs and the nearest competing FPGA. The x-axis shows the number of cores stamped for each of the seven OpenCore designs. Any data point above the 1.0 line indicates a Stratix III FPGA advantage in terms performance. To increase the design size (hence utilization), the number of stamps instantiated in the FPGA for each core was increased. As the number of stamps increases, the results show:
- The fMAX ratio increases because of a more rapid performance degradation in the nearest competing device. The performance advantage of the Stratix III FPGA increases up to 65 percent
- Quartus® II software exploits Altera's efficient FPGA architecture and uses the superior routing interconnects in Stratix III FPGAs to reach the most logic elements with fewest hops in high performance applications
Figure 1. Stratix III Performance Advantage Increases with Design Size (Utilization)
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Utilization Advantage
Figure 2 and Table 4 show the maximum number of cores that could be instantiated in the FPGA core. In terms of utilization, the results show:
- Stratix III FPGAs, on average, can fit 46 percent more logic than the nearest competing device
- Quartus II software maximizes utilization with the adaptive logic module (ALM) to implement logic functions, which is extremely efficient because of the ALM's fracturability
Figure 2. Stratix III FPGAs Fit More Logic on Comparable Devices
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| Table 4. Maximum Number of stamps Instantiated and Utilization |
| OpenCore Design |
Number of Cores
Stratix III 3SL340 |
Number of Cores
Virtex-5 V5LX330 |
Utilization Percentage
Stratix III 3SL340 |
Utilization Percentage
Virtex-5 V5LX330 |
| oc_aquarius |
50 |
15 |
91.0 |
28.0 |
| oc_des_des3perf |
30 |
10 |
100.0 |
43.9 |
| oc_ethernet |
115 |
90 |
99.0 |
89.0 |
| oc_oc8051 |
85 |
70 |
94.0 |
83.0 |
| oc_or1k |
40 |
20 |
92.0 |
45.5 |
| oc_pci |
110 |
70 |
98.0 |
75.0 |
| oc_usb_funct |
80 |
80 |
95.0 |
93.0 |
Table 5 shows the error codes received when attempting to increase the design size beyond the number of stamps shown above. Note that the nearest competing device often fails to compile prematurely with "no route” errors.
| Table 5. Error Code for Next Core Stamp |
| Design |
Error on Stratix III |
Error Code on Virtex-5 |
| oc_aquarius |
Not enough LABs(1) |
Not enough RAM |
| oc_des_des3perf |
Not enough LABs |
No route |
| oc_ethernet |
Not enough LABs |
No route |
| oc_oc8051 |
Not enough LABs |
No route |
| oc_or1k |
Not enough LABs |
No route |
| oc_pci |
Not enough RAM |
Not enough RAM |
| oc_usb_funct |
Not enough LABs |
Not enough slices |
Note:
- LABs = Logic array blocks
Compile Time Advantage
Figure 3 and Table 6 show a comparison in compile times limited by the maximum number of cores that could fit in the nearest competing device. In terms of compile times, the results show:
- Stratix III FPGAs compile 3x to 9x faster than the nearest competing device
Figure 3. Compile Time Comparison
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| Table 6. Compile Time Comparison |
| Designs |
Number of
Cores Stamped |
ISE, 9.2i SP4
(Hours) |
Quartus II, 8.0
(Hours) |
Quartus II vs. ISE |
| oc_aquarius |
15 |
6.53 |
0.99 |
6.6X Faster |
| oc_des_des3perf |
10 |
4.11 |
1.24 |
3.3X Faster |
| oc_ethernet |
90 |
14.48 |
2.2 |
6.6X Faster |
| oc_oc8051 |
70 |
16.35 |
2.85 |
5.7X Faster |
| oc_or1k |
20 |
5.98 |
1.64 |
3.6X Faster |
| oc_pci |
70 |
16.33 |
2.47 |
6.6X Faster |
| oc_usb_funct |
80 |
23.68 |
2.54 |
9.3X Faster |
Benchmarking and Stamping Methodology
All OpenCores benchmarking results are based on comparing an Altera® FPGA to the equivalent, nearest competing FPGA with comparable speed grades available in software.
To download the seven OpenCore designs and to view the individual design results, see Table 7.
Note:
- Please contact Altera for native synthesis design project files
Altera has a third-party, industry-expert-endorsed performance benchmarking methodology (PDF) , which is used to compare FPGA performance between families from a single FPGA vendor and with those of competitive solutions. This ensures a consistent benchmarking environment when testing Altera FPGAs and when comparing them to competitor FPGAs.
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