Termination Solutions in Stratix III Devices
As devices switch faster, signal integrity becomes crucial. Stratix® III FPGAs offer advanced on-chip termination (OCT) technology to further improve signal integrity and simplify printed circuit board (PCB) design.
- Revolutionary dynamically-controlled, on-chip terminations (dynamic OCT)
- All I/O banks support OCT
- Supports series, parallel, and differential OCTs
- All new digital automatic calibration circuitry
| Table 1. Benefits of Dynamic OCT |
| Benefit |
Description |
| Reduce Power Consumption |
Compared to conventional termination, dynamic OCT reduces power consumption significantly as it eliminates constant DC power on the bus. |
| Improved Signal Integrity |
Dynamic OCT provides proper line termination and impedance matching on bidirectional buses, which helps prevent reflections on the transmission line. |
| Simpler Board Design |
Dynamic OCT removes on-board termination resistor requirements, resulting in a simpler PCB layout. |
| Lower Cost |
With dynamic OCT, fewer resistors, fewer traces, and less space are needed on the board. Reducing your layout time and the number of components on the PCB can result in lower overall system costs. |
| Increased System Reliability |
System reliability increases because dynamic OCT reduces the number of components on the PCB. |
Dynamic OCT
Stratix III FPGAs are the first and only FPGA to offer dynamic OCT. Dynamic OCT enables series termination (RS) and parallel termination (RT ) to be dynamically turned on/off during the data transfer. This feature is especially useful when Stratix III FPGAs are used with external memory interfaces such as interfacing with DDR memories.
The series and parallel terminations are turned on or off depending on the read and write cycle of the interface. During the write cycle, the RS is turned on and the RT is turned off to match the line impedance. During the read cycle, the RS is turned off and the RT is turned on as the Stratix III FPGA implements the far-end termination of the bus. See Figure 1.
Figure 1. Dynamic OCT for Memory Interface
Digital Calibration Circuitry
The new digital calibration circuitry in all Stratix III FPGA I/O pins allow you to precisely control the impedance value of the OCT resistors.
- All I/O banks support OCT with automatic calibration
- Compensates impedance change due to temperature and voltage fluctuation
- Provides precise impedance control for series and parallel OCTs
- Calibration can be enabled by user-controlled signals during device operation or by default during device configuration
- Pull-up/pull-down external resistors required on board as reference
Series Termination
Stratix III FPGAs support on-chip series termination for LVTTL, LVCMOS, and SSTL single-ended I/O standards. OCT is provided at the output signal to match the impedance of the transmission line, typically 25 Ω or 50 Ω. You can use this termination in many general-purpose applications and to interface with external memories such as DDR SDRAM memories. The Stratix III FPGA series termination supports dynamic OCT, which is useful for bidirectional interfaces (see Figure 2).
Figure 2. Stratix III On-Chip Series Termination
Parallel Termination
Stratix III FPGAs support on-chip parallel termination. Parallel termination is extremely useful for applications such as interfacing with external memories where I/O standards such as HSTL and SSTL are used. Stratix III FPGA parallel termination supports dynamic OCT, which is useful for bidirectional interfaces (see Figure 3).
Figure 3. Stratix III On-Chip Parallel Termination
Differential Termination
Stratix III FPGAs support input on-chip differential termination for high-speed differential signals such as LVDS (see Figure 4).
Figure 4. On-Chip Differential Termination
In additional OCTs, Stratix III FPGAs also support external termination schemes, as shown in Table 2.
| Table 2. Termination Solutions Support |
| Termination Type |
On-Chip |
External |
| Series |
 |
|
| Parallel |
|
|
| Differential |
|
|
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