Stratix III FPGA Low Power Consumption Features
Stratix® III devices provide the highest performance in the industry while using 50 percent less power than previous generation FPGAs. View the Stratix III FPGA Programmable Power Technology Flash movie below for an introduction.
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For technical details on Stratix III device power and information on power estimation accuracy and management, refer to Table 1.
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Table 1. Stratix III Device Power Resources
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Technical Documentation
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Learn how your next-generation systems can take full advantage of these groundbreaking Stratix III FPGA power conservation innovations:
Programmable Power Technology
Available exclusively in Stratix III FPGAs, Programmable Power Technology enables every programmable logic array block (LAB), digital signal processing (DSP) block, and memory block to deliver high speed or low power, depending on your design requirements.
All other FPGAs contain blocks that are designed to run at only one speed—the highest possible speed—to support timing critical paths (as depicted by yellow blocks in Figure 1). Using the Programmable Power Technology in Stratix III FPGAs, all logic blocks in the array except those designated as timing critical are set to low-power mode (as depicted by blue blocks in Figure 1). With only the timing critical blocks set to high-speed mode, power dissipation in Stratix III devices is substantially reduced.
Figure 1. Standard FPGA Fabrics Compared to Stratix III FPGA Fabric With Programmable Power Technology
View the Stratix III FPGA Programmable Power Technology Flash movie for more detail.
Most designs have very few critical paths that need the highest performance logic to meet timing, while the majority of the design paths have ample excess slack (based on slack histograms on 71 customer designs). Quartus® II software uses the Stratix III Programmable Power Technology to automatically take advantage of the excess slack found on non-critical design paths and minimize power consumption while maintaining the highest performance possible in critical paths. For more information about design slack histogram analysis, refer to the Stratix III Programmable Power (PDF) white paper.
Selectable Core Voltage
Another unique Stratix III power feature (independent of Programmable Power Technology), called selectable core voltage, gives you the option of using a power saving 0.9-V core voltage. Designs needing the highest performance use the 1.1-V core voltage, while designs requiring minimum power consumption can use the 0.9-V core voltage. Note that Programmable Power Technology lowers power significantly, independent of which core voltage is used. For more information about selectable core voltage, refer to the Stratix III Programmable Power (PDF) white paper.
Process and Circuit Technologies
Stratix III devices utilize the latest process and circuit techniques along with major circuit and architecture innovations to minimize power and still deliver the highest performance of any FPGA. Some of the technologies employed in Stratix III FPGAs include multi-threshold transistors, variable gate-length transistors, low-k dielectric, triple-gate oxide (TGO), super-thin gate oxide, and strained silicon. For additional information on these process and circuit technologies, refer to the Stratix III Programmable Power (PDF) white paper.
Quartus II PowerPlay Power Analysis and Optimization Tool
The Quartus II PowerPlay power analysis and optimization tool helps keep the total power consumption of your designs to a minimum. Altera began offering advanced power optimization capabilities in Quartus II software in 2005, and it immediately provided an average 25 percent reduction in dynamic power in our customers’ designs.
Since then, the PowerPlay power analysis and optimization tool has been improved with the addition of intelligent decision making in synthesis, placement, and routing. Today, by working in conjunction with Programmable Power Technology in the Stratix III silicon, the power consumption minimizing capability of PowerPlay power optimization is the best it has ever been. To learn more, visit the Power Optimization for Stratix III FPGAs web page.
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