External Memory Device Interfaces in Stratix GX FPGAs
Altera® Stratix™ GX devices address increasing memory bandwidth requirements in two ways: by providing customers with abundant on-chip memory resources with the TriMatrix™ memory structure and through additional off-chip data storage with support for external memory interfaces. Users can connect Stratix GX devices to a wide range of the latest memory devices from leading vendors such as Micron Technology, Integrated Device Technology, and Samsung Electronics. Using a comprehensive, industry-leading solution—flexible Stratix GX devices and customizable intellectual property (IP)—designers can integrate high-density memory devices into complex system designs without degrading data access performance or increasing development time.
The rapid deployment of next-generation system architectures is accompanied by an increasing demand for total system memory bandwidth, which pushes I/O bandwidth and processing power requirements to new levels. New memory-intensive applications have prompted memory device makers to develop larger, more feature-rich devices that are capable of high-speed data transfer. As each designer's application requires specialized capabilities and features, memory devices have proliferated, each focusing on a specific aspect (such as speed, cost, or size).
Stratix GX devices support a wide variety of cutting-edge memory interfaces, as summarized in Table 1. More information about these memory device types can be found on the SRAM and DRAM web pages.
| Table 1. External Memory Interface Support in Stratix GX devices |
| External Memory Device |
Maximum Data Transfer Rate |
Memory Clock Speed |
| Single Data Rate (SDR) SDRAM |
200 Mbps |
200 MHz |
| Double Data Rate (DDR) SDRAM (1) |
400 Mbps |
200 MHz |
| DDR FCRAM |
400 Mbps |
200 MHz |
| Zero Bus Turnaround (ZBT) SRAM |
200 Mbps |
200 MHz |
| Quad Data Rate (QDR) SRAM |
668 Mbps |
167 MHz |
| QDRII SRAM |
668 Mbps |
167 MHz |
Note:
- Memory Solutions Center - DDR SDRAM provides access to technical documentation, IP cores and reference designs, software and tool support, demo boards, characterization report, presentations and articles on DDR SDRAM.
Optimized for Performance
Stratix GX devices are designed to reliably transfer data to and from external memory devices. Stratix GX devices include dedicated I/O features that ensure that all timing requirements are met and that performance is maximized. These features are outlined in Table 2.
| Table 2: Stratix GX Device I/O Features |
| Feature |
Benefit |
| Multi-Register I/O Elements (IOEs) |
- Input, output, and output enable (OE) registers maximize performance
- Simplify implementation of multi-data rate I/O functions
|
| Programmable Input Delays |
- Meet input timing requirements of DDR SDRAM devices
|
| Programmable ZBT Delay |
- Eliminates bus turnaround contention
|
| Dedicated Data Strobe (DQS) Circuitry |
- Synthesizes high-speed clock and DQS signals
- Minimizes clock skew between DQS and data DQ signals
- Shifts DQS signal for optimized clock and data alignment
|
| Positive Edge Alignment Circuitry |
- Ensures positive-edge clock interface with the logic array
|
The Stratix GX IOE is shown in Figure 1.
Figure 1: Stratix GX Device I/O Circuitry
In addition to the I/O interface-specific features, Stratix GX devices maximize memory interface performance using general-purpose programmable logic features as outlined in Table 3.
| Table 3: Stratix GX Device Features |
| Feature |
Benefit |
| Phase-Locked Loops (PLLs) |
- Synthesize high-speed clock and data strobe signals
- Perform precise phase shifting for clock and data alignment
|
| Terminator™ Technology |
- Eliminates signal reflection
- Improves signal integrity
- Simplifies overall printed circuit board (PCB) design
|
| Advanced Clock Networks |
- Provide global and localized clock resources
|
| I/O Banks |
- Support memory device-compatible I/O standards
- HSTL Class I & II
- SSTL-2 Class II
|
IP Optimized for Stratix GX Devices
Altera offers fully customizable IP megafunction controller cores developed and tested by Altera and Altera Megafunction Partners Program (AMPPSM) partners, available at the IP MegaStore™ web site. Altera also offers several memory controller design examples for users designing their own custom memory interfaces. These megafunctions will allow designers to quickly and easily incorporate the latest semiconductor memory technologies into their Stratix GX designs using an intuitive graphical user interface (GUI) from within the Quartus® II software.
Altera and AMPP Partners controller IP megafunctions:
Altera memory controller design example:
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