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TriMatrix Memory in Stratix GX Devices

Stratix GX™ devices feature the TriMatrix™ memory structure, composed of three sizes of embedded RAM blocks. TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and 512-Kbit M-RAM blocks, each of which can be configured to support a wide range of features. Offering up to 3.4 Mbits of RAM and up to 4 terabits per second of device memory bandwidth, the TriMatrix memory structure makes the Stratix GX device family a viable solution for memory-intensive applications.

TriMatrix memory offers different memory structures that can implement a wide variety of memory functions found in complex designs. Designers can use the smaller M512 RAM blocks for first-in first-out (FIFO) functions and clock domain buffering where memory bandwidth is critical. The revolutionary M-RAM blocks address the field programmable gate array (FPGA) requirement for large buffering applications such as IP packet buffering and system cache. The M4K blocks are ideal for medium-sized memory applications such as asynchronous transfer mode (ATM) cell processing. Figures 1 and 2 show the TriMatrix memory structure and a variety of its applications.

Figure 1. TriMatrix Memory Structure

Figure 1. TriMatrix Memory Structure

Figure 2. TriMatrix Memory Applications

Figure 2. TriMatrix Memory Applications

High Memory Bandwidth & Density

Stratix GX devices offer a high memory-to-logic ratio, made possible by the area-efficient M-RAM blocks. Just as importantly, Stratix GX devices offer the smaller M512 and M4K blocks with 18-bit- and 36-bit-wide data ports per block respectively. The M512 and M4K blocks represent large FPGA memory bandwidth, which makes them ideal for applications requiring extensive accessibility to the memory resources.

Memory bandwidth measures the amount of data that can pass through a memory block and is defined as the product of the memory data port width and performance of the RAM blocks. With over 14,000 data ports in the EP1SGX40D and EP1SGX40G devices -- each one capable of transferring data rates over 250 MHz -- Stratix GX devices provide significant memory bandwidth over 4 terabits per second (as shown in Table 1).

Table 1: Stratix GX Device Bandwidth (1)
Device Logic Elements
(LEs)
Transceiver Channels Total RAM Bits M-RAM Blocks
(512 Kbits)
M4K Blocks
(4 Kbits)
M512 Blocks
(512 Bits)
Total Memory Bandwidth
(Mbps)
EP1SGX10C 10,570 4 920,448 1 60 94 1,208,350
EP1SGX10D 10,570 8 920,448 1 60 94 1,208,350
EP1SGX25C 25,660 4 1,944,576 2 138 224 2,812,280
EP1SGX25D 25,660 8 1,944,576 2 138 224 2,812,280
EP1SGX25F 25,660 16 1,944,576 2 138 224 2,812,280
EP1SGX40D 41,250 8 3,423,744 4 183 384 4,280,440
EP1SGX40G 41,250 20 3,423,744 4 183 384 4,380,440

Notes:

  1. 1. Does not include additional bandwidth figures associated with external memory device interfaces.

The RAM blocks in the high-performance TriMatrix memory structure offer the following features:

  • True dual port for complex memory functions
  • Parity-bits
  • Embedded shift register functionality
  • Mixed-clock mode
  • Byte-enabled support
  • Mixed-width support
  • Configurable memory width dimensions for each of the RAM blocks (as shown in Table 2)
Table 2: TriMatrix Memory Features
Memory Feature M512 Blocks
512 Bits + parity
M4K Blocks
4 Kbits + parity
M-RAM Blocks
512 Kbits + parity
Maximum Performance 318 MHz (1) 291 MHz (2) 287 MHz (3)
True Dual-Port Memory
Simple Dual-Port memory
Single-Port Memory
Byte Enable
Parity Bits
Shift Register
Mixed-Clock Mode
Configurations 512 x 1
256 x 2
128 x 4
64 x 8
64 x 9
32 x 16
32 x 18
4K x 1
2K x 2
1K x 4
512 x 8
512 x 9
256 x 16
256 x 18
128 x 32
128 x 36
64K x 8
64K x 9
32K x 16
32K x 18
16K x 32
16K x 36
8K x 64
8K x 72
4K x 128
4K x 144

Notes:

  1. Configurations: Simple dual-port RAM 32 x 18 bit and FIFO 32 x 18 bit
  2. Configurations: Simple dual-port RAM 128 x 36 bit, true dual-port RAM 128 x 18 bit, and FIFO 128 x 36 bit
  3. Configuration: True dual-port RAM 32K x 9 bit

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