Transceiver Signal Integrity Development Kit, Stratix IV GX Edition

from Altera

Altera's Transceiver Signal Integrity Development Kit, Stratix^® IV GX Edition enables a thorough evaluation of transceiver interoperability and serializer/deserializer (SERDES) signal integrity by allowing you to:

• Evaluate transceiver performance from 600 Mbps to 8.5 Gbps
• Generate and check pseudo-random binary sequence (PRBS) patterns via a simple-to-use GUI (does not require Quartus^® II software)
• Dynamically change Voltage Output Differential (V_OD), pre-emphasis, and equalization settings to optimize transceiver performance for your channel
• Perform jitter analysis
• Verify physical medium attachment (PMA) compliance to PCI Express (Gen1 and Gen2), Serial RapidIO^®, Gigabit Ethernet, 10 Gigabit Ethernet XAUI, CEI-6G, Fibre Channel 1G/4G/8G, high-definition serial digital interface (HD-SDI), and other major standards

Ordering Information

Table 1. Altera's Transceiver SI Development Kit, Stratix IV GX Edition Ordering Information
Ordering Code	Price	Ordering Information
DK-SI-4SGX230N	$2,995	In North America, call 1-888-800-0631 or contact your local distributor. For International Sales, contact your local distributor.

Video: Analyze FPGA Transceiver Interoperability and Signal Integrity

Development Kit Contents

The Transceiver Signal Integrity Development Kit, Stratix IV GX Edition features the following:

• Stratix IV GX development board (see Figure 1)
  • Featured device
    • EP4SGX230KF40C2N
  • Configuration status and set-up elements
    • FPP configuration
    • Embedded USB-Blaster^TM download cable
  • Clocks
    • On-board clock oscillators: 50 MHz, 100 MHz, 156.25 MHz, 312.5 MHz, and
      425.0 MHz
    • SMA connectors for supplying an external differential clock to transceiver reference clock
    • SMA connectors for supplying an external differential clock to the FPGA fabric
    • SMA connectors to output a differential clock from the FPGA’s PLL output pin
  • General user input/output
    • DIP and push-button switches
    • LEDs
    • LCD
  • Memory devices
    • 64-MB sync flash memory (primarily to store FPGA configurations)
  • Components and interfaces
    • Eight full-duplex transceiver channels routed to SMA connectors
    • One micro-strip channel with minimal board trace length
    • Six strip-line channels from the same transceiver block; all the trace lengths are matched across channels
      • Four channels with full PMA+PCS functionality up to 8.5 Gbps
      • Two CMU channels with PMA functionality up to 6.375 Gbps
    • One long channel with ~33’’ trace length on transmit and ~7” trace length on receive to simulate the degradation associated with backplanes or long traces
    • Power measurement circuitry on transceiver-related supplies
    • The voltage on all (and only) these rails can be supplied via banana jacks
    • Temperature measurement circuitry
      • Die temperature
      • Ambient temperature
    • RJ-45 jack and 10/100/1000Base-T Ethernet PHY
• Application GUI
  • Platform independent
  • Interfaces to PC via JTAG
  • Embedded blaster
  • User controllable
    • V_OD and pre-emphasis settings
    • Equalizer setting
    • Test pattern
  • Status indicator
    • Number of errors
    • BER
    • Lock signal
• Quartus II software license is not included and is not required for kit evaluation

Figure 1. Stratix IV GX Transceiver Signal Integrity Development Board

For information on the Transceiver Signal Integrity Development Kit, Stratix IV GT (11.3 Gbps) Edition, please visit http://www.altera.com/products/devkits/altera/kit-stratix-iv-gt-si.html