Stratix III FPGA Development Kit

from Altera

The Stratix^® III FPGA Development Kit delivers a complete environment for the development and testing of designs requiring high-performance and high-density devices.

Altera^® Stratix III FPGAs combine the world's highest performance and highest density with the lowest possible power consumption. You'll find Stratix III FPGAs provide the high-performance and high-integration capabilities needed for next-generation basestations, network infrastructure, and advanced imaging equipment.

• Ordering information
• High-speed mezzanine card (HSMC) interface  
• Development kit contents
• Available documentation

Stratix III FPGA Development Kit Ordering Information

Table 1. Stratix III FPGA Development Kit Ordering Code and Pricing Information
Ordering Code	Price	Ordering Information
DK-DEV-3SL150N	$2,495	Contact your local Altera distributor to place your order.

HSMC Interface

Altera developed the specification for the HSMC interface, which is based on the Samtec mechanical connector, to define and standardize the interface between optional daughtercards and host boards. This specification outlines both the electrical and mechanical properties of the interface between daughtercard and host. You can also create your own HSMC interface compatible daughtercards.

• Download the HSMC Specification (PDF) data sheet

Stratix III FPGA Development Kit Contents

The Stratix III FPGA Development Kit is RoHS compliant and includes:

• Stratix III development board
  • Stratix III EP3SL150F1152 high-performance FPGA
    • 142,500 equivalent logic elements (LEs)
    • 744 user I/O pins
    • 384 18x18 multipliers
  • Clocking
    • 125-MHz oscillator
    • 50-MHz oscillator
    • SMA input
    • SMA output
  • Configuration
    • MAX^® II  flash passive serial configuration circuit
      • MAX II EPM2210GF256C3N CPLD
        • 2,210 LEs
        • 272 user I/O pins
        • 8-KB user flash memory
    • On-board USB-Blaster^TM download cable using Quartus^® II development software programming
    • JTAG download port
  • General user input and output
    • Power consumption display
      • Displays each power rail individually
    • System reset push button
    • Board-specific dual in-line package (DIP) switch
    • JTAG bypass DIP switch
    • User reset push button
    • User push buttons (x4)
    • User DIP switch (x8)
    • User LEDs (x8)
    • User quad 7-segment display
    • 128x64 dot pixels graphics display
    • LCD (16 character x 2 line)
  • Memory devices
    • 128-MB DDR2 SDRAM DIMM
    • 16-MB DDR2 SDRAM devices (individually addressable)
    • 36-Mb QDR II SRAM device
    • 4-MB PSRAM 
    • 64-MB flash memory
  • Components and interfaces
    • USB 2.0
    • 10/100/1000 Ethernet
    • Two HSMC interfaces
  • Power supplies
    • 12-A DC/DC µModule - LTM4601EV
    • 1.5-A low-input voltage VLDO linear regulator - LTC3026EDD
    • 100-mA, low-noise, LDO micropower regulators in SOT-23 - LT1761ES5-SD
    • 4.5-A, 500-kHz step-down switching regulator - LT1374CFE
    • 1.2-MHz/2.2-MHz inverting DC/DC converters in ThinSOT - LT1931AES5
    • 1-/2-channel 24-bit µPower no latency delta-sigma ADC in MSOP-10 - LTC2402CMS
• Quartus II development kit software, including a one-year license
• Cable and accessories  
  • External AC adapter power supply
  • Power cord (including support for UK, Europe)

Available Documentation

Note:

1. This kit installation works with Quartus II development kit software version 9.1 SP2.

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Related Links

• Literature for Stratix III FPGAs 
• Stratix III DSP Development Kit
• Power Management Center for Altera devices