Transceiver Signal Integrity Development Kit, Stratix IV GT Edition

from Altera

Altera's Transceiver Signal Integrity Development Kit, Stratix^® IV GT Edition enables a thorough evaluation of transceiver interoperability and serializer/deserializer (SERDES) signal integrity by allowing you to:

• Evaluate transceiver performance up to 11.3 Gbps
• Generate and check pseudo-random binary sequence (PRBS) patterns via a simple-to-use GUI (does not require Quartus^® II software)
• Dynamically change differential output voltage (V_OD), pre-emphasis, and equalization settings to optimize transceiver performance for your channel
• Perform jitter analysis
• Verify physical medium attachment (PMA) compliance to 40G/100G Ethernet, Interlaken, CEI-6G/11G, PCI Express^® (Gen1, Gen2, and Gen3), Serial RapidIO^®, and other major standards
• Validate interoperability between optical modules (optical modules require SMA input to test interoperability with the Transceiver Signal Integrity Development Kit, Stratix IV GT Edition), such as SFP, SFP+, and QSFP

Ordering Information

Table 1. Altera's Transceiver Signal Integrity Development Kit, Stratix IV GT Edition Ordering Information
Ordering Code	Price	Ordering Information
DK-SI-4S100G2N	$7,995	In North America, call 1-888-800-0631 or contact your local distributor. For international sales, contact your local distributor.

Development Kit Contents

The Transceiver Signal Integrity Development Kit, Stratix IV GT Edition has the following features:

• Stratix IV GT development board (see Figure 1)
  • Featured device
    • EP4S100G2F40I1N
  • Configuration status and set-up elements
    • Fast passive parallel (FPP) configuration
    • Embedded USB-Blaster^TM download cable
• Clocks
  • Onboard clock oscillators: 50 MHz, 100 MHz, 644.53 MHz, and 706.25 MHz
  • SMA connectors for supplying an external differential clock to transceiver reference clock
• General user input and output
  • Dual in-line package (DIP) and push-button switches
  • LEDs
  • LCD
• Memory devices
  • 64-MB sync flash memory (primarily to store FPGA configurations)
• Components and interfaces
  • Six full-duplex transceiver channels routed to SMA connectors
    • All channels support up to 11.3-Gbps data rate
  • Six full-duplex transceiver channels routed to FCI Airmax connector
  • Power measurement circuitry on transceiver-related supplies
  • The voltage on all (and only) these rails can be supplied via banana jacks
  • Temperature measurement circuitry
    • Die temperature
    • Ambient temperature
  • RJ-45 jack and 10/100/1000Base-T Ethernet PHY
• Backplane drive capability at 6.5 Gbps
  • Directly connect the transceiver signal integrity development kit to an FCI backplane (not included) through the FCI connector header
  • Couple with a second signal integrity development kit or FCI daughtercard (not included) for a complete end-to-end backplane channel analysis
• Application GUI
  • Platform independent
  • Interfaces to PC via JTAG
  • Embedded blaster
  • User controllable
    • V_OD and pre-emphasis settings
    • Equalizer setting
    • Test pattern
  • Status indicator
    • Number of errors
    • Bit-error rate (BER)
    • Lock signal
  • EyeQ reconstructs the eye width in the device receiver for monitoring signal quality after equalization (up to 6 Gbps)
• Quartus II software license is not included and is not required for kit evaluation

Figure 1. Stratix IV GT Development Board

For information on the Transceiver Signal Integrity Development Kit, Stratix IV GX (8.5 Gbps) Edition, please visit www.altera.com/sikit.