The phase-locked loop (PLL) is used many applications from cellular base stations to industrial systems and processes. A PLL is a feedback system that, under certain given conditions, dynamically reduces phase and/or frequency offset between a received signal and a locally generated carrier to zero. This is of crucial importance in communications systems receivers that suffer degradation in demodulated signal to noise ratio (SNR) due to phase error. The All-digital phase locked loop (ADPLL) is a phase lock loop implemented in purely digital circuitry and operating on finite precision digital words. A block diagram is shown in Figure 1.
Figure 1. ADPLL Block Diagram
The phase detector deduces the difference in phase between its two input signals. Phase detectors can be implemented in numerous ways, including an XOR gate implementation, a J/K flipflop phase detector, a digital multiplier, Nyquist-rate phase detector (NRPD), or a Hilbert transform phase detector. This reference design uses a digital multiplier that outputs a DC term proportional to the phase difference and series of higher frequency components. The high-frequency terms arising from multiplication in the phase detector are filtered out by the loop filter. The loop filter is usually a first or second order infinite impulse response (IIR) low-pass filter. The filter output is passed to the numerically controlled oscillator (NCO), adjusts phase and frequency to reduce phase error to zero, a condition known as phase lock.
For the locked condition to be attainable, the frequency of the reference signal must be within a defined distance from the free-running or open loop frequency of the NCO, known as the pull-in range. Another important parameter is the hold range, which defines how large the frequency deviation can be between the two signals before they unlock. The amount of time required for the loop to become locked is known as the pull-in time. These parameters can be strictly controlled by modifying the loop bandwidth of the ADPLL.
Design Files Provided
The ADPLL reference design files are located in the \refdesigns\pll\* folder. Table 1 describes the files provided with this reference design.
To download the reference design files, go to the NCO product page and click on the free test drive icon.
| Table 1. ADPLL Reference Design Files | |
| File | Description |
| pll.gdf | Top-level design file, which can be compiled and simulated in the MAX+PLUS® II or QuartusTM II software. |
| tbpll.v | Verilog HDL testbench, which writes the input reference sinusoid and the locked output sinusoid to text files. |
| adpll.mdl | Simulink model of the ADPLL, which can be used to test the IIR loop filter response for different design specifications. |
The testbench instantiates a second NCO to generate the reference input sinusoid to which the loop locks.
Functional Description
In this design, an 8-bit digital multiplier is used as the phase detector. The loop filter is a first-order IIR digital filter resulting in a second order ADPLL overall. The NCO uses a small internal ROM-based architecture with a frequency modulation input and the following parameters:
- Phase accumulator width: 24
- ROM address width: 10
- Magnitude precision: 8
- Frequency modulation input width: 16
The output of the loop filter shifts the input free-running phase increment to the NCO (via its frequency modulation input) hence shifting its output frequency toward that of the input reference. This ADPLL has a free-running frequency of 40 kHz, a pull-in range of at least 3 kHz, and an acquisition time of 250 µs.
Using a multiplier as a phase detector gives a locked condition with a 90 degrees phase offset. You can compensate for the shift by initially passing the reference input signal through a Hilbert transformer, which has a magnitude response of 1 but shifts the phase of any signal by -90 degrees.
