Recent years have shown a rapid development of I/O and board-to-board protocols in the communications sector. The development, evolution, and adoption of these protocols led to the need for them to communicate with each other and with devices that use other protocols.
Altera is committed to providing interoperability-tested, high-performance, standard interface intellectual property (IP) cores, allowing designers to use protocols such as POS-PHY, UTOPIA, Flexbus, RapidIO, and HyperTransport. With the introduction of the Atlantic standard on-chip interface, designers can bridge different I/O standards simply by wiring Atlantic signals together.
Altera's standardized Atlantic datapath interface simplifies the task of bridging otherwise-incompatible devices. The Atlantic bus is a simple supported, on-chip datapath bus that enables the rapid integration of IP cores. An example is shown in Figure 1.
Figure 1: XSBI to SPI-4.2 Bridge Using the Atlantic Interface
The Atlantic interface is a scalable, high-speed on-chip interface for packet and cell transfer. Optimized for programmable logic devices (PLDs), the Atlantic interface allows designers to quickly and easily join incompatible devices and facilitate the user's IP integration with a simple, clearly defined, and supported interface.
The Atlantic interface is a synchronous point-to-point connection for packet-oriented data. Its scalable clock frequency and data bus width allow for high throughput of arbitrary length packets. The Atlantic interface supports master source-to-slave sink, or master sink-to-slave source relationships. The control signals and fixed start of packet (SOP) alignment simplify packet handling and allow flexible flow control. The block diagram in Figure 2 shows both relationships and their respective control signals.
Figure 2. Atlantic Block Diagram
For more information about Altera's Atlantic on-chip interface, or to become an Atlantic partner, please contact Altera® Applications at http://www.altera.com/mysupport.
