Altera's FLEX, APEX, and ACEX devices contain fully-parameterizable embedded memory in embedded system blocks for simple integration and fast access. For programmable logic designs requiring external memory, memory controllers are available as intellectual property megafunctions from Altera and Altera Megafunction Partners Program (AMPP) partners. These megafunctions allow designers to quickly and easily interface their programmable logic device (PLD) designs with the latest semiconductor memory technologies. In addition, Altera offers memory controller reference designs for users to design their own custom memory interfaces.
SDRAM
Synchronous dynamic random access memory (SDRAM) is high-speed dynamic random access memory (DRAM). If used efficiently, the synchronous interface and fully pipelined internal architecture of SDRAM allows extremely fast data rates.
Single data rate (SDR) SDRAM features a fully synchronous interface, where all signals are referenced to the positive clock edge. SDR speeds support system clock frequencies of 66 MHz, 100 MHz, and 133 MHz. Internally pipelined operation allows column addresses to be changed at every clock cycle, and multiple internal banks allow interleaving to help hide row access and pre-charge times.
Double data rate (DDR) SDRAM samples data at both the rising and falling edges of the clock. DDR speeds support system clock frequencies of 100 MHz, 133 MHz, and 143 MHz. A bidirectional datastrobe signal is added, which toggles at the same frequency as the system clock and provides a good clock edge to the sample data. DDR SDRAM modules feature on-chip delay-locked loops to align data with the system clock at high speeds.
Simulation models for SDR and DDR SDRAM modules are available from Micron.
CAM
Content-addressable memory (CAM) devices are increasingly used in high-performance router table implementations for asynchronous transfer mode (ATM) and Ethernet applications. Binary CAM devices and newer ternary CAM devices offer one-cycle searches allowing more cost-effective, centralized processing architectures to be implemented. In addition, today's CAM devices are fully synchronous, allowing easy interface to other devices in the system.
Subnetting is a secondary structure commonly used within an Internet protocol network consisting of several physical subnets. The subnet boundary is represented as a bit mask, and in routing tables using subnets it is necessary to maintain the subnet mask information. The bit masking capability in ternary CAM devices makes the CAM extremely useful not only for subnet masking, but also for classless interdomain routing implementation (used in determining the longest prefix match).
